Move the 'meta' dir to 'lib/cretonne/meta'.

The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.

This is in preparation for publishing crates on crates.io.

lib/cretonne/meta/isa/riscv/__init__.py

@@ -0,0 +1,32 @@
+"""
+RISC-V Target
+-------------
+
+`RISC-V <http://riscv.org/>`_ is an open instruction set architecture
+originally developed at UC Berkeley. It is a RISC-style ISA with either a
+32-bit (RV32I) or 64-bit (RV32I) base instruction set and a number of optional
+extensions:
+
+RV32M / RV64M
+    Integer multiplication and division.
+
+RV32A / RV64A
+    Atomics.
+
+RV32F / RV64F
+    Single-precision IEEE floating point.
+
+RV32D / RV64D
+    Double-precision IEEE floating point.
+
+RV32G / RV64G
+    General purpose instruction sets. This represents the union of the I, M, A,
+    F, and D instruction sets listed above.
+
+"""
+from __future__ import absolute_import
+from . import defs
+from . import encodings, settings # noqa
+
+# Re-export the primary target ISA definition.
+isa = defs.isa.finish()

lib/cretonne/meta/isa/riscv/defs.py

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+"""
+RISC-V definitions.
+
+Commonly used definitions.
+"""
+from __future__ import absolute_import
+from cretonne import TargetISA, CPUMode
+import cretonne.base
+
+isa = TargetISA('riscv', [cretonne.base.instructions])
+
+# CPU modes for 32-bit and 64-bit operation.
+RV32 = CPUMode('RV32', isa)
+RV64 = CPUMode('RV64', isa)

lib/cretonne/meta/isa/riscv/encodings.py

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+"""
+RISC-V Encodings.
+"""
+from __future__ import absolute_import
+from cretonne import base
+from .defs import RV32, RV64
+from .recipes import OPIMM, OPIMM32, OP, OP32, R, Rshamt, I
+from .settings import use_m
+
+# Basic arithmetic binary instructions are encoded in an R-type instruction.
+for inst,           inst_imm,      f3,    f7 in [
+        (base.iadd, base.iadd_imm, 0b000, 0b0000000),
+        (base.isub, None,          0b000, 0b0100000),
+        (base.bxor, base.bxor_imm, 0b100, 0b0000000),
+        (base.bor,  base.bor_imm,  0b110, 0b0000000),
+        (base.band, base.band_imm, 0b111, 0b0000000)
+        ]:
+    RV32.enc(inst.i32, R, OP(f3, f7))
+    RV64.enc(inst.i64, R, OP(f3, f7))
+
+    # Immediate versions for add/xor/or/and.
+    if inst_imm:
+        RV32.enc(inst_imm.i32, I, OPIMM(f3))
+        RV64.enc(inst_imm.i64, I, OPIMM(f3))
+
+# 32-bit ops in RV64.
+RV64.enc(base.iadd.i32, R, OP32(0b000, 0b0000000))
+RV64.enc(base.isub.i32, R, OP32(0b000, 0b0100000))
+# There are no andiw/oriw/xoriw variations.
+RV64.enc(base.iadd_imm.i32, I, OPIMM32(0b000))
+
+# Dynamic shifts have the same masking semantics as the cton base instructions.
+for inst,           inst_imm,      f3,    f7 in [
+        (base.ishl, base.ishl_imm, 0b001, 0b0000000),
+        (base.ushr, base.ushr_imm, 0b101, 0b0000000),
+        (base.sshr, base.sshr_imm, 0b101, 0b0100000),
+        ]:
+    RV32.enc(inst.i32.i32, R, OP(f3, f7))
+    RV64.enc(inst.i64.i64, R, OP(f3, f7))
+    RV64.enc(inst.i32.i32, R, OP32(f3, f7))
+    # Allow i32 shift amounts in 64-bit shifts.
+    RV64.enc(inst.i64.i32, R, OP(f3, f7))
+    RV64.enc(inst.i32.i64, R, OP32(f3, f7))
+
+    # Immediate shifts.
+    RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
+    RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
+    RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))
+
+# "M" Standard Extension for Integer Multiplication and Division.
+# Gated by the `use_m` flag.
+RV32.enc(base.imul.i32, R, OP(0b000, 0b0000001), isap=use_m)
+RV64.enc(base.imul.i64, R, OP(0b000, 0b0000001), isap=use_m)
+RV64.enc(base.imul.i32, R, OP32(0b000, 0b0000001), isap=use_m)

lib/cretonne/meta/isa/riscv/recipes.py

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+"""
+RISC-V Encoding recipes.
+
+The encoding recipes defined here more or less correspond to the RISC-V native
+instruction formats described in the reference:
+
+    The RISC-V Instruction Set Manual
+    Volume I: User-Level ISA
+    Version 2.1
+"""
+from __future__ import absolute_import
+from cretonne import EncRecipe
+from cretonne.formats import Binary, BinaryImm
+from cretonne.predicates import IsSignedInt
+
+# The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
+# instructions have 11 as the two low bits, with bits 6:2 determining the base
+# opcode.
+#
+# Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ...
+# The functions below encode the encbits.
+
+
+def LOAD(funct3):
+    assert funct3 <= 0b111
+    return 0b00000 | (funct3 << 5)
+
+
+def STORE(funct3):
+    assert funct3 <= 0b111
+    return 0b01000 | (funct3 << 5)
+
+
+def BRANCH(funct3):
+    assert funct3 <= 0b111
+    return 0b11000 | (funct3 << 5)
+
+
+def OPIMM(funct3, funct7=0):
+    assert funct3 <= 0b111
+    return 0b00100 | (funct3 << 5) | (funct7 << 8)
+
+
+def OPIMM32(funct3, funct7=0):
+    assert funct3 <= 0b111
+    return 0b00110 | (funct3 << 5) | (funct7 << 8)
+
+
+def OP(funct3, funct7):
+    assert funct3 <= 0b111
+    assert funct7 <= 0b1111111
+    return 0b01100 | (funct3 << 5) | (funct7 << 8)
+
+
+def OP32(funct3, funct7):
+    assert funct3 <= 0b111
+    assert funct7 <= 0b1111111
+    return 0b01110 | (funct3 << 5) | (funct7 << 8)
+
+
+# R-type 32-bit instructions: These are mostly binary arithmetic instructions.
+# The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
+R = EncRecipe('R', Binary)
+
+# R-type with an immediate shift amount instead of rs2.
+Rshamt = EncRecipe('Rshamt', BinaryImm)
+
+I = EncRecipe('I', BinaryImm, instp=IsSignedInt(BinaryImm.imm, 12))

lib/cretonne/meta/isa/riscv/settings.py

@@ -0,0 +1,28 @@
+"""
+RISC-V settings.
+"""
+from __future__ import absolute_import
+from cretonne import SettingGroup, BoolSetting
+from cretonne.predicates import And
+import cretonne.settings as shared
+from .defs import isa
+
+isa.settings = SettingGroup('riscv', parent=shared.group)
+
+supports_m = BoolSetting("CPU supports the 'M' extension (mul/div)")
+supports_a = BoolSetting("CPU supports the 'A' extension (atomics)")
+supports_f = BoolSetting("CPU supports the 'F' extension (float)")
+supports_d = BoolSetting("CPU supports the 'D' extension (double)")
+
+enable_m = BoolSetting(
+        "Enable the use of 'M' instructions if available",
+        default=True)
+
+use_m = And(supports_m, enable_m)
+use_a = And(supports_a, shared.enable_atomics)
+use_f = And(supports_f, shared.enable_float)
+use_d = And(supports_d, shared.enable_float)
+
+full_float = And(shared.enable_simd, supports_f, supports_d)
+
+isa.settings.close(globals())