Generate register class descriptors.

Add a mechanism for defining sub-classes of register classes.

lib/cretonne/meta/gen_registers.py

@@ -8,7 +8,7 @@ import srcgen
 try:
     from typing import Sequence  # noqa
     from cdsl.isa import TargetISA  # noqa
-    from cdsl.registers import RegBank  # noqa
+    from cdsl.registers import RegBank, RegClass  # noqa
 except ImportError:
     pass
 
@@ -18,8 +18,7 @@ def gen_regbank(regbank, fmt):
     """
     Emit a static data definition for regbank.
     """
-    with fmt.indented(
-            'RegBank {{'.format(regbank.name), '},'):
+    with fmt.indented('RegBank {', '},'):
         fmt.line('name: "{}",'.format(regbank.name))
         fmt.line('first_unit: {},'.format(regbank.first_unit))
         fmt.line('units: {},'.format(regbank.units))
@@ -29,6 +28,19 @@ def gen_regbank(regbank, fmt):
         fmt.line('prefix: "{}",'.format(regbank.prefix))
 
 
+def gen_regclass(idx, rc, fmt):
+    # type: (int, RegClass, srcgen.Formatter) -> None
+    """
+    Emit a static data definition for a register class.
+    """
+    fmt.comment(rc.name)
+    with fmt.indented('RegClassData {', '},'):
+        fmt.line('index: {},'.format(idx))
+        fmt.line('width: {},'.format(rc.width))
+        mask = ', '.join('0x{:08x}'.format(x) for x in rc.mask())
+        fmt.line('mask: [{}],'.format(mask))
+
+
 def gen_isa(isa, fmt):
     # type: (TargetISA, srcgen.Formatter) -> None
     """
@@ -36,11 +48,29 @@ def gen_isa(isa, fmt):
     """
     if not isa.regbanks:
         print('cargo:warning={} has no register banks'.format(isa.name))
+
+    rcs = list()  # type: List[RegClass]
     with fmt.indented('pub static INFO: RegInfo = RegInfo {', '};'):
         # Bank descriptors.
         with fmt.indented('banks: &[', '],'):
             for regbank in isa.regbanks:
                 gen_regbank(regbank, fmt)
+                rcs += regbank.classes
+        fmt.line('classes: &CLASSES,')
+
+    # Register class descriptors.
+    with fmt.indented(
+            'const CLASSES: [RegClassData; {}] = ['.format(len(rcs)), '];'):
+        for idx, rc in enumerate(rcs):
+            gen_regclass(idx, rc, fmt)
+
+    # Emit constants referencing the register classes.
+    for idx, rc in enumerate(rcs):
+        if rc.name:
+            fmt.line('#[allow(dead_code)]')
+            fmt.line(
+                    'pub const {}: RegClass = &CLASSES[{}];'
+                    .format(rc.name, idx))
 
 
 def generate(isas, out_dir):