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[build] Introduce a TargetIsaBuilder to better encapsulate the TargetIsa;

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It was the caller's responsibility to call TargetIsa::check() before;
now one can't manipulate a TargetIsa without calling the
TargetIsaBuilder::finish() method, which is less error-prone and more in
line with what's coming for other things we're going to generate in the
meta crate.

Also splits the construction of a RegClass in two parts: a prototype is
made first when declaring the RegClass, and missing bits are filled in
when adding it to the TargetIsa(Builder). This avoids an awkward passing
of the isa to the RegClass ctor.
This commit is contained in:
Benjamin Bouvier
2018-11-08 18:41:15 +01:00
committed by Dan Gohman
parent f896bfb946
commit add4043bb5
7 changed files with 108 additions and 104 deletions
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18
lib/codegen/meta/src/isa/arm32/mod.rs
View File

@@ -1,8 +1,8 @@
use cdsl::isa::{TargetIsa, TargetIsaBuilder};
use cdsl::regs::{RegBankBuilder, RegClassBuilder};
use isa;
pub fn define() -> isa::TargetIsa {
let mut isa = isa::TargetIsa::new("arm32");
pub fn define() -> TargetIsa {
let mut isa = TargetIsaBuilder::new("arm32");
let builder = RegBankBuilder::new("FloatRegs", "s")
.units(64)
@@ -20,20 +20,20 @@ pub fn define() -> isa::TargetIsa {
.track_pressure(false);
let flag_reg = isa.add_reg_bank(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "S", float_regs).count(32);
let builder = RegClassBuilder::new_toplevel("S", float_regs).count(32);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "D", float_regs).width(2);
let builder = RegClassBuilder::new_toplevel("D", float_regs).width(2);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "Q", float_regs).width(4);
let builder = RegClassBuilder::new_toplevel("Q", float_regs).width(4);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "GPR", int_regs);
let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "FLAG", flag_reg);
let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
isa.add_reg_class(builder);
isa
isa.finish()
}

14
lib/codegen/meta/src/isa/arm64/mod.rs
View File

@@ -1,8 +1,8 @@
use cdsl::isa::{TargetIsa, TargetIsaBuilder};
use cdsl::regs::{RegBankBuilder, RegClassBuilder};
use isa;
pub fn define() -> isa::TargetIsa {
let mut isa = isa::TargetIsa::new("arm64");
pub fn define() -> TargetIsa {
let mut isa = TargetIsaBuilder::new("arm64");
// The `x31` regunit serves as the stack pointer / zero register depending on context. We
// reserve it and don't model the difference.
@@ -22,14 +22,14 @@ pub fn define() -> isa::TargetIsa {
.track_pressure(false);
let flag_reg = isa.add_reg_bank(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "GPR", int_regs);
let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "FPR", float_regs);
let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "FLAG", flag_reg);
let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
isa.add_reg_class(builder);
isa
isa.finish()
}

8
lib/codegen/meta/src/isa/mod.rs
View File

@@ -62,14 +62,10 @@ impl fmt::Display for Isa {
}
pub fn define_all() -> Vec<TargetIsa> {
let isas = vec![
vec![
riscv::define(),
arm32::define(),
arm64::define(),
x86::define(),
];
for isa in isas.iter() {
isa.check();
}
isas
]
}

12
lib/codegen/meta/src/isa/riscv/mod.rs
View File

@@ -1,8 +1,8 @@
use cdsl::isa::{TargetIsa, TargetIsaBuilder};
use cdsl::regs::{RegBankBuilder, RegClassBuilder};
use isa;
pub fn define() -> isa::TargetIsa {
let mut isa = isa::TargetIsa::new("riscv");
pub fn define() -> TargetIsa {
let mut isa = TargetIsaBuilder::new("riscv");
let builder = RegBankBuilder::new("IntRegs", "x")
.units(32)
@@ -14,11 +14,11 @@ pub fn define() -> isa::TargetIsa {
.track_pressure(true);
let float_regs = isa.add_reg_bank(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "GPR", int_regs);
let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "FPR", float_regs);
let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
isa.add_reg_class(builder);
isa
isa.finish()
}

20
lib/codegen/meta/src/isa/x86/mod.rs
View File

@@ -1,8 +1,8 @@
use cdsl::isa::{TargetIsa, TargetIsaBuilder};
use cdsl::regs::{RegBankBuilder, RegClassBuilder};
use isa;
pub fn define() -> isa::TargetIsa {
let mut isa = isa::TargetIsa::new("x86");
pub fn define() -> TargetIsa {
let mut isa = TargetIsaBuilder::new("x86");
let builder = RegBankBuilder::new("IntRegs", "r")
.units(16)
@@ -21,23 +21,23 @@ pub fn define() -> isa::TargetIsa {
.track_pressure(false);
let flag_reg = isa.add_reg_bank(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "GPR", int_regs);
let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
let gpr = isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "FPR", float_regs);
let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
let fpr = isa.add_reg_class(builder);
let builder = RegClassBuilder::new_toplevel(&mut isa, "FLAG", flag_reg);
let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
isa.add_reg_class(builder);
let builder = RegClassBuilder::subclass_of(&mut isa, "GPR8", gpr, 0, 8);
let builder = RegClassBuilder::subclass_of("GPR8", gpr, 0, 8);
let gpr8 = isa.add_reg_class(builder);
let builder = RegClassBuilder::subclass_of(&mut isa, "ABCD", gpr8, 0, 4);
let builder = RegClassBuilder::subclass_of("ABCD", gpr8, 0, 4);
isa.add_reg_class(builder);
let builder = RegClassBuilder::subclass_of(&mut isa, "FPR8", fpr, 0, 8);
let builder = RegClassBuilder::subclass_of("FPR8", fpr, 0, 8);
isa.add_reg_class(builder);
isa
isa.finish()
}