Move constant instructions into meta.

Add new immediate types for floating point and vector immediates.
Use new immediates to define the constant value instructions in meta.

Split the fconst instruction into two: f32const and f64const. This prevents
confusion about the interpretation of 64 immediate bits when generating an f32
constant.

Add an immvector ImmediateType. This immediate type is variable length, and
provides all the bits of a SIMD vector directly.

cranelift/docs/cton_lexer.py

@@ -23,7 +23,7 @@ class CretonneLexer(RegexLexer):
             # Numbers.
             (r'[-+]?0[xX][0-9a-fA-F]+', Number.Hex),
             (r'[-+]?0[xX][0-9a-fA-F]*\.[0-9a-fA-F]*([pP]\d+)?', Number.Hex),
-            (r'[-+]?\d+\.\d+([eE]\d+)?', Number.Float),
+            (r'[-+]?(\d+\.\d+([eE]\d+)?|[sq]NaN|Inf)', Number.Float),
             (r'[-+]?\d+', Number.Integer),
             # Reserved words.
             (keywords('function', 'entry'), Keyword),

cranelift/docs/example.cton

@@ -2,7 +2,7 @@ function average(i32, i32) -> f32 {
     ss1 = stack_slot 8, align 4   ; Stack slot for ``sum``.
 
 entry ebb1(v1: i32, v2: i32):
-    v3 = fconst.f64 0.0
+    v3 = f64const 0x0.0
     stack_store v3, ss1
     brz v2, ebb3                  ; Handle count == 0.
     v4 = iconst.i32 0
@@ -26,6 +26,6 @@ ebb2(v5: i32):
     return v17
 
 ebb3:
-    v100 = fconst.f32 0x7fc00000  ; 0/0 = NaN
+    v100 = f32const qNaN
     return v100
 }

cranelift/docs/langref.rst

@@ -212,6 +212,23 @@ indicate the different kinds of immediate operands on an instruction.
     signed two's complement integer. Instruction encodings may limit the valid
     range.
 
+.. type:: ieee32
+
+    A 32-bit immediate floating point number in the IEEE 754-2008 binary32
+    interchange format. All bit patterns are allowed.
+
+.. type:: ieee64
+
+    A 64-bit immediate floating point number in the IEEE 754-2008 binary64
+    interchange format. All bit patterns are allowed.
+
+.. type:: immvector
+
+    An immediate SIMD vector. This operand supplies all the bits of a SIMD
+    type, so it can have different sizes depending on the type produced. The
+    bits of the operand are interpreted as if the SIMD vector was loaded from
+    memory containing the immediate.
+
 Control flow
 ============
 
@@ -628,31 +645,10 @@ A few instructions have variants that take immediate operands (e.g.,
 :inst:`band` / :inst:`band_imm`), but in general an instruction is required to
 load a constant into an SSA value.
 
-.. inst:: a = iconst N
+.. autoinst:: iconst
-
+.. autoinst:: f32const
-    Integer constant.
+.. autoinst:: f64const
-
+.. autoinst:: vconst
-    Create a scalar integer SSA value with an immediate constant value, or an
-    integer vector where all the lanes have the same value.
-
-    :result Int a: Constant value.
-
-.. inst:: a = fconst N
-
-    Floating point constant.
-
-    Create a :type:`f32` or :type:`f64` SSA value with an immediate constant
-    value, or a floating point vector where all the lanes have the same value.
-
-    :result Float a: Constant value.
-
-.. inst:: a = vconst N
-
-    Vector constant (floating point or integer).
-
-    Create a SIMD vector value where the lanes don't have to be identical.
-
-    :result TxN a: Constant value.
 
 .. inst:: a = select c, x, y
 

meta/cretonne/base.py

@@ -4,11 +4,59 @@ Cretonne base instruction set.
 This module defines the basic Cretonne instruction set that all targets support.
 """
 from . import TypeVar, Operand, Instruction
-from types import i8
+from types import i8, f32, f64
-from immediates import imm64
+from immediates import imm64, ieee32, ieee64, immvector
 
 Int = TypeVar('Int', 'A scalar or vector integer type')
 iB = TypeVar('iB', 'A scalar integer type')
+TxN = TypeVar('%Tx%N', 'A SIMD vector type')
+
+#
+# Materializing constants.
+#
+
+N = Operand('N', imm64)
+a = Operand('a', Int, doc='A constant integer scalar or vector value')
+iconst = Instruction('iconst', r"""
+    Integer constant.
+
+    Create a scalar integer SSA value with an immediate constant value, or an
+    integer vector where all the lanes have the same value.
+    """,
+    ins=N, outs=a)
+
+N = Operand('N', ieee32)
+a = Operand('a', f32, doc='A constant integer scalar or vector value')
+f32const = Instruction('f32const', r"""
+    Floating point constant.
+
+    Create a :type:`f32` SSA value with an immediate constant value, or a
+    floating point vector where all the lanes have the same value.
+    """,
+    ins=N, outs=a)
+
+N = Operand('N', ieee64)
+a = Operand('a', f64, doc='A constant integer scalar or vector value')
+f64const = Instruction('f64const', r"""
+    Floating point constant.
+
+    Create a :type:`f64` SSA value with an immediate constant value, or a
+    floating point vector where all the lanes have the same value.
+    """,
+    ins=N, outs=a)
+
+N = Operand('N', immvector)
+a = Operand('a', TxN, doc='A constant vector value')
+vconst = Instruction('vconst', r"""
+    Vector constant (floating point or integer).
+
+    Create a SIMD vector value where the lanes don't have to be identical.
+    """,
+    ins=N, outs=a)
+
+#
+# Integer arithmetic
+#
 
 a = Operand('a', Int)
 x = Operand('x', Int)

meta/cretonne/immediates.py

@@ -10,3 +10,16 @@ from . import ImmediateType
 #: This type of immediate integer can interact with SSA values with any
 #: :py:class:`cretonne.IntType` type.
 imm64 = ImmediateType('imm64', 'A 64-bit immediate integer.')
+
+#: A 32-bit immediate floating point operand.
+#:
+#: IEEE 754-2008 binary32 interchange format.
+ieee32 = ImmediateType('ieee32', 'A 32-bit immediate floating point number.')
+
+#: A 64-bit immediate floating point operand.
+#:
+#: IEEE 754-2008 binary64 interchange format.
+ieee64 = ImmediateType('ieee64', 'A 64-bit immediate floating point number.')
+
+#: A large SIMD vector constant.
+immvector = ImmediateType('immvector', 'An immediate SIMD vector.')