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[AArch64] Port IaddPairwise to ISLE (#4201)

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-06-06 15:37:13 +01:00
committed by GitHub
parent 7148882867
commit acfeda4d80
7 changed files with 150 additions and 50 deletions
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21
cranelift/codegen/src/isa/aarch64/lower.isle
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@@ -99,6 +99,27 @@
(add_with_flags_paired $I64 x_lo y_lo)
(adc_paired $I64 x_hi y_hi))))
;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $I16X8 (iadd_pairwise (swiden_low x) (swiden_high y))))
(if-let z (same_value x y))
(saddlp8 z))
(rule (lower (has_type $I32X4 (iadd_pairwise (swiden_low x) (swiden_high y))))
(if-let z (same_value x y))
(saddlp16 z))
(rule (lower (has_type $I16X8 (iadd_pairwise (uwiden_low x) (uwiden_high y))))
(if-let z (same_value x y))
(uaddlp8 z))
(rule (lower (has_type $I32X4 (iadd_pairwise (uwiden_low x) (uwiden_high y))))
(if-let z (same_value x y))
(uaddlp16 z))
(rule (lower (has_type ty (iadd_pairwise x y)))
(addp x y (vector_size ty)))
;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; `i64` and smaller