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cranelift: Add shifts and extends to fuzzer (#4700)

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* cranelift: Remove shifts-small-types runtests

These were moved to the main shifts file in #4519 but this file was accidentaly left in tree.

It also fixes the missing sshr_i8_i8 testcase

* cranelift: Add shifts to fuzzer

* cranelift: Add extends to fuzzer
This commit is contained in:
Afonso Bordado
2022-08-12 01:57:00 +01:00
committed by GitHub
parent 532fb22af6
commit ac9725840d
3 changed files with 108 additions and 327 deletions
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322
cranelift/filetests/filetests/runtests/shifts-small-types.clif
View File

@@ -1,322 +0,0 @@
test run
target aarch64
target s390x
; TODO: Merge this with the main shifts file when x86_64 passes these.
function %ishl_i16_i64(i16, i64) -> i16 {
block0(v0: i16, v1: i64):
v2 = ishl.i16 v0, v1
return v2
}
; run: %ishl_i16_i64(0x0000, 0) == 0x0000
; run: %ishl_i16_i64(0x0000, 1) == 0x0000
; run: %ishl_i16_i64(0x000f, 0) == 0x000f
; run: %ishl_i16_i64(0x000f, 4) == 0x00f0
; run: %ishl_i16_i64(0x0004, 16) == 0x0004
; run: %ishl_i16_i64(0x0004, 17) == 0x0008
; run: %ishl_i16_i64(0x0004, 18) == 0x0010
function %ishl_i16_i32(i16, i32) -> i16 {
block0(v0: i16, v1: i32):
v2 = ishl.i16 v0, v1
return v2
}
; run: %ishl_i16_i32(0x0000, 0) == 0x0000
; run: %ishl_i16_i32(0x0000, 1) == 0x0000
; run: %ishl_i16_i32(0x000f, 0) == 0x000f
; run: %ishl_i16_i32(0x000f, 4) == 0x00f0
; run: %ishl_i16_i32(0x0004, 16) == 0x0004
; run: %ishl_i16_i32(0x0004, 17) == 0x0008
; run: %ishl_i16_i32(0x0004, 18) == 0x0010
function %ishl_i16_i16(i16, i16) -> i16 {
block0(v0: i16, v1: i16):
v2 = ishl.i16 v0, v1
return v2
}
; run: %ishl_i16_i16(0x0000, 0) == 0x0000
; run: %ishl_i16_i16(0x0000, 1) == 0x0000
; run: %ishl_i16_i16(0x000f, 0) == 0x000f
; run: %ishl_i16_i16(0x000f, 4) == 0x00f0
; run: %ishl_i16_i16(0x0004, 16) == 0x0004
; run: %ishl_i16_i16(0x0004, 17) == 0x0008
; run: %ishl_i16_i16(0x0004, 18) == 0x0010
function %ishl_i16_i8(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
v2 = ishl.i16 v0, v1
return v2
}
; run: %ishl_i16_i8(0x0000, 0) == 0x0000
; run: %ishl_i16_i8(0x0000, 1) == 0x0000
; run: %ishl_i16_i8(0x000f, 0) == 0x000f
; run: %ishl_i16_i8(0x000f, 4) == 0x00f0
; run: %ishl_i16_i8(0x0004, 16) == 0x0004
; run: %ishl_i16_i8(0x0004, 17) == 0x0008
; run: %ishl_i16_i8(0x0004, 18) == 0x0010
function %ishl_i8_i64(i8, i64) -> i8 {
block0(v0: i8, v1: i64):
v2 = ishl.i8 v0, v1
return v2
}
; run: %ishl_i8_i64(0x00, 0) == 0x00
; run: %ishl_i8_i64(0x00, 1) == 0x00
; run: %ishl_i8_i64(0x0f, 0) == 0x0f
; run: %ishl_i8_i64(0x0f, 4) == 0xf0
; run: %ishl_i8_i64(0x04, 8) == 0x04
; run: %ishl_i8_i64(0x04, 9) == 0x08
; run: %ishl_i8_i64(0x04, 10) == 0x10
function %ishl_i8_i32(i8, i32) -> i8 {
block0(v0: i8, v1: i32):
v2 = ishl.i8 v0, v1
return v2
}
; run: %ishl_i8_i32(0x00, 0) == 0x00
; run: %ishl_i8_i32(0x00, 1) == 0x00
; run: %ishl_i8_i32(0x0f, 0) == 0x0f
; run: %ishl_i8_i32(0x0f, 4) == 0xf0
; run: %ishl_i8_i32(0x04, 8) == 0x04
; run: %ishl_i8_i32(0x04, 9) == 0x08
; run: %ishl_i8_i32(0x04, 10) == 0x10
function %ishl_i8_i16(i8, i16) -> i8 {
block0(v0: i8, v1: i16):
v2 = ishl.i8 v0, v1
return v2
}
; run: %ishl_i8_i16(0x00, 0) == 0x00
; run: %ishl_i8_i16(0x00, 1) == 0x00
; run: %ishl_i8_i16(0x0f, 0) == 0x0f
; run: %ishl_i8_i16(0x0f, 4) == 0xf0
; run: %ishl_i8_i16(0x04, 8) == 0x04
; run: %ishl_i8_i16(0x04, 9) == 0x08
; run: %ishl_i8_i16(0x04, 10) == 0x10
function %ishl_i8_i8(i8, i8) -> i8 {
block0(v0: i8, v1: i8):
v2 = ishl.i8 v0, v1
return v2
}
; run: %ishl_i8_i8(0x00, 0) == 0x00
; run: %ishl_i8_i8(0x00, 1) == 0x00
; run: %ishl_i8_i8(0x0f, 0) == 0x0f
; run: %ishl_i8_i8(0x0f, 4) == 0xf0
; run: %ishl_i8_i8(0x04, 8) == 0x04
; run: %ishl_i8_i8(0x04, 9) == 0x08
; run: %ishl_i8_i8(0x04, 10) == 0x10
function %ushr_i16_i64(i16, i64) -> i16 {
block0(v0: i16, v1: i64):
v2 = ushr.i16 v0, v1
return v2
}
; run: %ushr_i16_i64(0x1000, 0) == 0x1000
; run: %ushr_i16_i64(0x1000, 1) == 0x0800
; run: %ushr_i16_i64(0xf000, 0) == 0xf000
; run: %ushr_i16_i64(0xf000, 4) == 0x0f00
; run: %ushr_i16_i64(0x4000, 16) == 0x4000
; run: %ushr_i16_i64(0x4000, 17) == 0x2000
; run: %ushr_i16_i64(0x4000, 18) == 0x1000
function %ushr_i16_i32(i16, i32) -> i16 {
block0(v0: i16, v1: i32):
v2 = ushr.i16 v0, v1
return v2
}
; run: %ushr_i16_i32(0x1000, 0) == 0x1000
; run: %ushr_i16_i32(0x1000, 1) == 0x0800
; run: %ushr_i16_i32(0xf000, 0) == 0xf000
; run: %ushr_i16_i32(0xf000, 4) == 0x0f00
; run: %ushr_i16_i32(0x4000, 16) == 0x4000
; run: %ushr_i16_i32(0x4000, 17) == 0x2000
; run: %ushr_i16_i32(0x4000, 18) == 0x1000
function %ushr_i16_i16(i16, i16) -> i16 {
block0(v0: i16, v1: i16):
v2 = ushr.i16 v0, v1
return v2
}
; run: %ushr_i16_i16(0x1000, 0) == 0x1000
; run: %ushr_i16_i16(0x1000, 1) == 0x0800
; run: %ushr_i16_i16(0xf000, 0) == 0xf000
; run: %ushr_i16_i16(0xf000, 4) == 0x0f00
; run: %ushr_i16_i16(0x4000, 16) == 0x4000
; run: %ushr_i16_i16(0x4000, 17) == 0x2000
; run: %ushr_i16_i16(0x4000, 18) == 0x1000
function %ushr_i16_i8(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
v2 = ushr.i16 v0, v1
return v2
}
; run: %ushr_i16_i8(0x1000, 0) == 0x1000
; run: %ushr_i16_i8(0x1000, 1) == 0x0800
; run: %ushr_i16_i8(0xf000, 0) == 0xf000
; run: %ushr_i16_i8(0xf000, 4) == 0x0f00
; run: %ushr_i16_i8(0x4000, 16) == 0x4000
; run: %ushr_i16_i8(0x4000, 17) == 0x2000
; run: %ushr_i16_i8(0x4000, 18) == 0x1000
function %ushr_i8_i64(i8, i64) -> i8 {
block0(v0: i8, v1: i64):
v2 = ushr.i8 v0, v1
return v2
}
; run: %ushr_i8_i64(0x10, 0) == 0x10
; run: %ushr_i8_i64(0x10, 1) == 0x08
; run: %ushr_i8_i64(0xf0, 0) == 0xf0
; run: %ushr_i8_i64(0xf0, 4) == 0x0f
; run: %ushr_i8_i64(0x40, 8) == 0x40
; run: %ushr_i8_i64(0x40, 9) == 0x20
; run: %ushr_i8_i64(0x40, 10) == 0x10
function %ushr_i8_i32(i8, i32) -> i8 {
block0(v0: i8, v1: i32):
v2 = ushr.i8 v0, v1
return v2
}
; run: %ushr_i8_i32(0x10, 0) == 0x10
; run: %ushr_i8_i32(0x10, 1) == 0x08
; run: %ushr_i8_i32(0xf0, 0) == 0xf0
; run: %ushr_i8_i32(0xf0, 4) == 0x0f
; run: %ushr_i8_i32(0x40, 8) == 0x40
; run: %ushr_i8_i32(0x40, 9) == 0x20
; run: %ushr_i8_i32(0x40, 10) == 0x10
function %ushr_i8_i16(i8, i16) -> i8 {
block0(v0: i8, v1: i16):
v2 = ushr.i8 v0, v1
return v2
}
; run: %ushr_i8_i16(0x10, 0) == 0x10
; run: %ushr_i8_i16(0x10, 1) == 0x08
; run: %ushr_i8_i16(0xf0, 0) == 0xf0
; run: %ushr_i8_i16(0xf0, 4) == 0x0f
; run: %ushr_i8_i16(0x40, 8) == 0x40
; run: %ushr_i8_i16(0x40, 9) == 0x20
; run: %ushr_i8_i16(0x40, 10) == 0x10
function %ushr_i8_i8(i8, i8) -> i8 {
block0(v0: i8, v1: i8):
v2 = ushr.i8 v0, v1
return v2
}
; run: %ushr_i8_i8(0x10, 0) == 0x10
; run: %ushr_i8_i8(0x10, 1) == 0x08
; run: %ushr_i8_i8(0xf0, 0) == 0xf0
; run: %ushr_i8_i8(0xf0, 4) == 0x0f
; run: %ushr_i8_i8(0x40, 8) == 0x40
; run: %ushr_i8_i8(0x40, 9) == 0x20
; run: %ushr_i8_i8(0x40, 10) == 0x10
function %sshr_i16_i64(i16, i64) -> i16 {
block0(v0: i16, v1: i64):
v2 = sshr.i16 v0, v1
return v2
}
; run: %sshr_i16_i64(0x8000, 0) == 0x8000
; run: %sshr_i16_i64(0x8000, 1) == 0xC000
; run: %sshr_i16_i64(0xf000, 0) == 0xf000
; run: %sshr_i16_i64(0xf000, 4) == 0xff00
; run: %sshr_i16_i64(0x4000, 16) == 0x4000
; run: %sshr_i16_i64(0x4000, 17) == 0x2000
; run: %sshr_i16_i64(0x4000, 18) == 0x1000
function %sshr_i16_i32(i16, i32) -> i16 {
block0(v0: i16, v1: i32):
v2 = sshr.i16 v0, v1
return v2
}
; run: %sshr_i16_i32(0x8000, 0) == 0x8000
; run: %sshr_i16_i32(0x8000, 1) == 0xC000
; run: %sshr_i16_i32(0xf000, 0) == 0xf000
; run: %sshr_i16_i32(0xf000, 4) == 0xff00
; run: %sshr_i16_i32(0x4000, 16) == 0x4000
; run: %sshr_i16_i32(0x4000, 17) == 0x2000
; run: %sshr_i16_i32(0x4000, 18) == 0x1000
function %sshr_i16_i16(i16, i16) -> i16 {
block0(v0: i16, v1: i16):
v2 = sshr.i16 v0, v1
return v2
}
; run: %sshr_i16_i16(0x8000, 0) == 0x8000
; run: %sshr_i16_i16(0x8000, 1) == 0xC000
; run: %sshr_i16_i16(0xf000, 0) == 0xf000
; run: %sshr_i16_i16(0xf000, 4) == 0xff00
; run: %sshr_i16_i16(0x4000, 16) == 0x4000
; run: %sshr_i16_i16(0x4000, 17) == 0x2000
; run: %sshr_i16_i16(0x4000, 18) == 0x1000
function %sshr_i16_i8(i16, i8) -> i16 {
block0(v0: i16, v1: i8):
v2 = sshr.i16 v0, v1
return v2
}
; run: %sshr_i16_i8(0x8000, 0) == 0x8000
; run: %sshr_i16_i8(0x8000, 1) == 0xC000
; run: %sshr_i16_i8(0xf000, 0) == 0xf000
; run: %sshr_i16_i8(0xf000, 4) == 0xff00
; run: %sshr_i16_i8(0x4000, 16) == 0x4000
; run: %sshr_i16_i8(0x4000, 17) == 0x2000
; run: %sshr_i16_i8(0x4000, 18) == 0x1000
function %sshr_i8_i64(i8, i64) -> i8 {
block0(v0: i8, v1: i64):
v2 = sshr.i8 v0, v1
return v2
}
; run: %sshr_i8_i64(0x80, 0) == 0x80
; run: %sshr_i8_i64(0x80, 1) == 0xC0
; run: %sshr_i8_i64(0xf0, 0) == 0xf0
; run: %sshr_i8_i64(0xf0, 4) == 0xff
; run: %sshr_i8_i64(0x40, 8) == 0x40
; run: %sshr_i8_i64(0x40, 9) == 0x20
; run: %sshr_i8_i64(0x40, 10) == 0x10
function %sshr_i8_i32(i8, i32) -> i8 {
block0(v0: i8, v1: i32):
v2 = sshr.i8 v0, v1
return v2
}
; run: %sshr_i8_i32(0x80, 0) == 0x80
; run: %sshr_i8_i32(0x80, 1) == 0xC0
; run: %sshr_i8_i32(0xf0, 0) == 0xf0
; run: %sshr_i8_i32(0xf0, 4) == 0xff
; run: %sshr_i8_i32(0x40, 8) == 0x40
; run: %sshr_i8_i32(0x40, 9) == 0x20
; run: %sshr_i8_i32(0x40, 10) == 0x10
function %sshr_i8_i16(i8, i16) -> i8 {
block0(v0: i8, v1: i16):
v2 = sshr.i8 v0, v1
return v2
}
; run: %sshr_i8_i16(0x80, 0) == 0x80
; run: %sshr_i8_i16(0x80, 1) == 0xC0
; run: %sshr_i8_i16(0xf0, 0) == 0xf0
; run: %sshr_i8_i16(0xf0, 4) == 0xff
; run: %sshr_i8_i16(0x40, 8) == 0x40
; run: %sshr_i8_i16(0x40, 9) == 0x20
; run: %sshr_i8_i16(0x40, 10) == 0x10
function %sshr_i8_i64(i8, i64) -> i8 {
block0(v0: i8, v1: i64):
v2 = sshr.i8 v0, v1
return v2
}
; run: %sshr_i8_i64(0x80, 0) == 0x80
; run: %sshr_i8_i64(0x80, 1) == 0xC0
; run: %sshr_i8_i64(0xf0, 0) == 0xf0
; run: %sshr_i8_i64(0xf0, 4) == 0xff
; run: %sshr_i8_i64(0x40, 8) == 0x40
; run: %sshr_i8_i64(0x40, 9) == 0x20
; run: %sshr_i8_i64(0x40, 10) == 0x10

10
cranelift/filetests/filetests/runtests/shifts.clif
View File

@@ -627,15 +627,15 @@ block0(v0: i8, v1: i16):
; run: %sshr_i8_i16(0x40, 33) == 0x20 ; run: %sshr_i8_i16(0x40, 33) == 0x20
; run: %sshr_i8_i16(0x40, 34) == 0x10 ; run: %sshr_i8_i16(0x40, 34) == 0x10
function %sshr_i8_i8(i16, i8) -> i16 { function %sshr_i8_i8(i8, i8) -> i8 {
block0(v0: i16, v1: i8): block0(v0: i8, v1: i8):
v2 = sshr.i16 v0, v1 v2 = sshr.i8 v0, v1
return v2 return v2
} }
; run: %sshr_i8_i8(0x80, 0) == 0x80 ; run: %sshr_i8_i8(0x80, 0) == 0x80
; run: %sshr_i8_i8(0x80, 1) == 0x40 ; run: %sshr_i8_i8(0x80, 1) == 0xC0
; run: %sshr_i8_i8(0xf0, 0) == 0xf0 ; run: %sshr_i8_i8(0xf0, 0) == 0xf0
; run: %sshr_i8_i8(0xf0, 4) == 0x0f ; run: %sshr_i8_i8(0xf0, 4) == 0xff
; run: %sshr_i8_i8(0x40, 32) == 0x40 ; run: %sshr_i8_i8(0x40, 32) == 0x40
; run: %sshr_i8_i8(0x40, 33) == 0x20 ; run: %sshr_i8_i8(0x40, 33) == 0x20
; run: %sshr_i8_i8(0x40, 34) == 0x10 ; run: %sshr_i8_i8(0x40, 34) == 0x10

103
cranelift/fuzzgen/src/function_generator.rs
View File

@@ -193,6 +193,109 @@ const OPCODE_SIGNATURES: &'static [(
(Opcode::Rotl, &[I128, I32], &[I128], insert_opcode), (Opcode::Rotl, &[I128, I32], &[I128], insert_opcode),
(Opcode::Rotl, &[I128, I64], &[I128], insert_opcode), (Opcode::Rotl, &[I128, I64], &[I128], insert_opcode),
(Opcode::Rotl, &[I128, I128], &[I128], insert_opcode), (Opcode::Rotl, &[I128, I128], &[I128], insert_opcode),
// Ishl
// Some test cases disabled due to: https://github.com/bytecodealliance/wasmtime/issues/4699
(Opcode::Ishl, &[I8, I8], &[I8], insert_opcode),
(Opcode::Ishl, &[I8, I16], &[I8], insert_opcode),
(Opcode::Ishl, &[I8, I32], &[I8], insert_opcode),
(Opcode::Ishl, &[I8, I64], &[I8], insert_opcode),
// (Opcode::Ishl, &[I8, I128], &[I8], insert_opcode),
(Opcode::Ishl, &[I16, I8], &[I16], insert_opcode),
(Opcode::Ishl, &[I16, I16], &[I16], insert_opcode),
(Opcode::Ishl, &[I16, I32], &[I16], insert_opcode),
(Opcode::Ishl, &[I16, I64], &[I16], insert_opcode),
// (Opcode::Ishl, &[I16, I128], &[I16], insert_opcode),
(Opcode::Ishl, &[I32, I8], &[I32], insert_opcode),
(Opcode::Ishl, &[I32, I16], &[I32], insert_opcode),
(Opcode::Ishl, &[I32, I32], &[I32], insert_opcode),
(Opcode::Ishl, &[I32, I64], &[I32], insert_opcode),
(Opcode::Ishl, &[I32, I128], &[I32], insert_opcode),
(Opcode::Ishl, &[I64, I8], &[I64], insert_opcode),
(Opcode::Ishl, &[I64, I16], &[I64], insert_opcode),
(Opcode::Ishl, &[I64, I32], &[I64], insert_opcode),
(Opcode::Ishl, &[I64, I64], &[I64], insert_opcode),
(Opcode::Ishl, &[I64, I128], &[I64], insert_opcode),
(Opcode::Ishl, &[I128, I8], &[I128], insert_opcode),
(Opcode::Ishl, &[I128, I16], &[I128], insert_opcode),
(Opcode::Ishl, &[I128, I32], &[I128], insert_opcode),
(Opcode::Ishl, &[I128, I64], &[I128], insert_opcode),
(Opcode::Ishl, &[I128, I128], &[I128], insert_opcode),
// Sshr
// Some test cases disabled due to: https://github.com/bytecodealliance/wasmtime/issues/4699
(Opcode::Sshr, &[I8, I8], &[I8], insert_opcode),
(Opcode::Sshr, &[I8, I16], &[I8], insert_opcode),
(Opcode::Sshr, &[I8, I32], &[I8], insert_opcode),
(Opcode::Sshr, &[I8, I64], &[I8], insert_opcode),
// (Opcode::Sshr, &[I8, I128], &[I8], insert_opcode),
(Opcode::Sshr, &[I16, I8], &[I16], insert_opcode),
(Opcode::Sshr, &[I16, I16], &[I16], insert_opcode),
(Opcode::Sshr, &[I16, I32], &[I16], insert_opcode),
(Opcode::Sshr, &[I16, I64], &[I16], insert_opcode),
// (Opcode::Sshr, &[I16, I128], &[I16], insert_opcode),
(Opcode::Sshr, &[I32, I8], &[I32], insert_opcode),
(Opcode::Sshr, &[I32, I16], &[I32], insert_opcode),
(Opcode::Sshr, &[I32, I32], &[I32], insert_opcode),
(Opcode::Sshr, &[I32, I64], &[I32], insert_opcode),
(Opcode::Sshr, &[I32, I128], &[I32], insert_opcode),
(Opcode::Sshr, &[I64, I8], &[I64], insert_opcode),
(Opcode::Sshr, &[I64, I16], &[I64], insert_opcode),
(Opcode::Sshr, &[I64, I32], &[I64], insert_opcode),
(Opcode::Sshr, &[I64, I64], &[I64], insert_opcode),
(Opcode::Sshr, &[I64, I128], &[I64], insert_opcode),
(Opcode::Sshr, &[I128, I8], &[I128], insert_opcode),
(Opcode::Sshr, &[I128, I16], &[I128], insert_opcode),
(Opcode::Sshr, &[I128, I32], &[I128], insert_opcode),
(Opcode::Sshr, &[I128, I64], &[I128], insert_opcode),
(Opcode::Sshr, &[I128, I128], &[I128], insert_opcode),
// Ushr
// Some test cases disabled due to: https://github.com/bytecodealliance/wasmtime/issues/4699
(Opcode::Ushr, &[I8, I8], &[I8], insert_opcode),
(Opcode::Ushr, &[I8, I16], &[I8], insert_opcode),
(Opcode::Ushr, &[I8, I32], &[I8], insert_opcode),
(Opcode::Ushr, &[I8, I64], &[I8], insert_opcode),
// (Opcode::Ushr, &[I8, I128], &[I8], insert_opcode),
(Opcode::Ushr, &[I16, I8], &[I16], insert_opcode),
(Opcode::Ushr, &[I16, I16], &[I16], insert_opcode),
(Opcode::Ushr, &[I16, I32], &[I16], insert_opcode),
(Opcode::Ushr, &[I16, I64], &[I16], insert_opcode),
// (Opcode::Ushr, &[I16, I128], &[I16], insert_opcode),
(Opcode::Ushr, &[I32, I8], &[I32], insert_opcode),
(Opcode::Ushr, &[I32, I16], &[I32], insert_opcode),
(Opcode::Ushr, &[I32, I32], &[I32], insert_opcode),
(Opcode::Ushr, &[I32, I64], &[I32], insert_opcode),
(Opcode::Ushr, &[I32, I128], &[I32], insert_opcode),
(Opcode::Ushr, &[I64, I8], &[I64], insert_opcode),
(Opcode::Ushr, &[I64, I16], &[I64], insert_opcode),
(Opcode::Ushr, &[I64, I32], &[I64], insert_opcode),
(Opcode::Ushr, &[I64, I64], &[I64], insert_opcode),
(Opcode::Ushr, &[I64, I128], &[I64], insert_opcode),
(Opcode::Ushr, &[I128, I8], &[I128], insert_opcode),
(Opcode::Ushr, &[I128, I16], &[I128], insert_opcode),
(Opcode::Ushr, &[I128, I32], &[I128], insert_opcode),
(Opcode::Ushr, &[I128, I64], &[I128], insert_opcode),
(Opcode::Ushr, &[I128, I128], &[I128], insert_opcode),
// Uextend
(Opcode::Uextend, &[I8], &[I16], insert_opcode),
(Opcode::Uextend, &[I8], &[I32], insert_opcode),
(Opcode::Uextend, &[I8], &[I64], insert_opcode),
(Opcode::Uextend, &[I8], &[I128], insert_opcode),
(Opcode::Uextend, &[I16], &[I32], insert_opcode),
(Opcode::Uextend, &[I16], &[I64], insert_opcode),
(Opcode::Uextend, &[I16], &[I128], insert_opcode),
(Opcode::Uextend, &[I32], &[I64], insert_opcode),
(Opcode::Uextend, &[I32], &[I128], insert_opcode),
(Opcode::Uextend, &[I64], &[I128], insert_opcode),
// Sextend
(Opcode::Sextend, &[I8], &[I16], insert_opcode),
(Opcode::Sextend, &[I8], &[I32], insert_opcode),
(Opcode::Sextend, &[I8], &[I64], insert_opcode),
(Opcode::Sextend, &[I8], &[I128], insert_opcode),
(Opcode::Sextend, &[I16], &[I32], insert_opcode),
(Opcode::Sextend, &[I16], &[I64], insert_opcode),
(Opcode::Sextend, &[I16], &[I128], insert_opcode),
(Opcode::Sextend, &[I32], &[I64], insert_opcode),
(Opcode::Sextend, &[I32], &[I128], insert_opcode),
(Opcode::Sextend, &[I64], &[I128], insert_opcode),
// Fadd // Fadd
(Opcode::Fadd, &[F32, F32], &[F32], insert_opcode), (Opcode::Fadd, &[F32, F32], &[F32], insert_opcode),
(Opcode::Fadd, &[F64, F64], &[F64], insert_opcode), (Opcode::Fadd, &[F64, F64], &[F64], insert_opcode),