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Add an Intel-specific x86_cvtt2si instruction.

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This is used to represent the non-trapping semantics of the cvttss2si and
cvttsd2si instructions (and their vectorized counterparts).

The overflow behavior of this instruction is specific to the Intel ISAs.

There is no float-to-i64 instruction on the 32-bit Intel ISA.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-26 15:35:32 -07:00
parent d13f29cfe4
commit ac69f3bfdf
5 changed files with 77 additions and 0 deletions
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24
cranelift/filetests/isa/intel/binary64-float.cton
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@@ -96,6 +96,18 @@ ebb0:
; asm: movaps %xmm5, %xmm10
[-,%xmm10] v39 = copy v10 ; bin: 44 0f 28 d5
; Convert float to int.
; asm: cvttss2si %xmm5, %ecx
[-,%rcx] v40 = x86_cvtt2si.i32 v10 ; bin: f3 0f 2c cd
; asm: cvttss2si %xmm10, %esi
[-,%rsi] v41 = x86_cvtt2si.i32 v11 ; bin: f3 41 0f 2c f2
; asm: cvttss2si %xmm5, %rcx
[-,%rcx] v42 = x86_cvtt2si.i64 v10 ; bin: f3 48 0f 2c cd
; asm: cvttss2si %xmm10, %rsi
[-,%rsi] v43 = x86_cvtt2si.i64 v11 ; bin: f3 49 0f 2c f2
; Unary arithmetic.
; asm: sqrtss %xmm5, %xmm10
@@ -291,6 +303,18 @@ ebb0:
; asm: movaps %xmm5, %xmm10
[-,%xmm10] v39 = copy v10 ; bin: 44 0f 28 d5
; Convert float to int.
; asm: cvttsd2si %xmm5, %ecx
[-,%rcx] v40 = x86_cvtt2si.i32 v10 ; bin: f2 0f 2c cd
; asm: cvttsd2si %xmm10, %esi
[-,%rsi] v41 = x86_cvtt2si.i32 v11 ; bin: f2 41 0f 2c f2
; asm: cvttsd2si %xmm5, %rcx
[-,%rcx] v42 = x86_cvtt2si.i64 v10 ; bin: f2 48 0f 2c cd
; asm: cvttsd2si %xmm10, %rsi
[-,%rsi] v43 = x86_cvtt2si.i64 v11 ; bin: f2 49 0f 2c f2
; Unary arithmetic.
; asm: sqrtsd %xmm5, %xmm10