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Make the fst recipe use the deref-safe register class as well.

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This commit is contained in:
Dan Gohman
2018-02-28 10:12:40 -08:00
parent 9010e576dd
commit ab9298eafa
2 changed files with 11 additions and 1 deletions
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10
cranelift/filetests/isa/intel/binary64-float.cton
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@@ -20,6 +20,7 @@ ebb0:
[-,%rsi] v1 = iconst.i32 2 [-,%rsi] v1 = iconst.i32 2
[-,%rax] v2 = iconst.i64 11 [-,%rax] v2 = iconst.i64 11
[-,%r14] v3 = iconst.i64 12 [-,%r14] v3 = iconst.i64 12
[-,%r13] v4 = iconst.i64 13
; asm: cvtsi2ssl %r11d, %xmm5 ; asm: cvtsi2ssl %r11d, %xmm5
[-,%xmm5] v10 = fcvt_from_sint.f32 v0 ; bin: f3 41 0f 2a eb [-,%xmm5] v10 = fcvt_from_sint.f32 v0 ; bin: f3 41 0f 2a eb
@@ -173,6 +174,10 @@ ebb0:
[-] store.f32 v100, v3 ; bin: 66 41 0f 7e 2e [-] store.f32 v100, v3 ; bin: 66 41 0f 7e 2e
; asm: movd %xmm10, (%rax) ; asm: movd %xmm10, (%rax)
[-] store.f32 v101, v2 ; bin: 66 44 0f 7e 10 [-] store.f32 v101, v2 ; bin: 66 44 0f 7e 10
; asm: movd %xmm5, (%r13)
[-] store.f32 v100, v4 ; bin: 66 41 0f 7e 6d 00
; asm: movd %xmm10, (%r13)
[-] store.f32 v101, v4 ; bin: 66 45 0f 7e 55 00
; asm: movd %xmm5, 50(%r14) ; asm: movd %xmm5, 50(%r14)
[-] store.f32 v100, v3+50 ; bin: 66 41 0f 7e 6e 32 [-] store.f32 v100, v3+50 ; bin: 66 41 0f 7e 6e 32
; asm: movd %xmm10, -50(%rax) ; asm: movd %xmm10, -50(%rax)
@@ -250,6 +255,7 @@ ebb0:
[-,%rsi] v1 = iconst.i32 2 [-,%rsi] v1 = iconst.i32 2
[-,%rax] v2 = iconst.i64 11 [-,%rax] v2 = iconst.i64 11
[-,%r14] v3 = iconst.i64 12 [-,%r14] v3 = iconst.i64 12
[-,%r13] v4 = iconst.i64 13
; asm: cvtsi2sdl %r11d, %xmm5 ; asm: cvtsi2sdl %r11d, %xmm5
[-,%xmm5] v10 = fcvt_from_sint.f64 v0 ; bin: f2 41 0f 2a eb [-,%xmm5] v10 = fcvt_from_sint.f64 v0 ; bin: f2 41 0f 2a eb
@@ -403,6 +409,10 @@ ebb0:
[-] store.f64 v100, v3 ; bin: 66 41 0f d6 2e [-] store.f64 v100, v3 ; bin: 66 41 0f d6 2e
; asm: movq %xmm10, (%rax) ; asm: movq %xmm10, (%rax)
[-] store.f64 v101, v2 ; bin: 66 44 0f d6 10 [-] store.f64 v101, v2 ; bin: 66 44 0f d6 10
; asm: movq %xmm5, (%r13)
[-] store.f64 v100, v4 ; bin: 66 41 0f d6 6d 00
; asm: movq %xmm10, (%r13)
[-] store.f64 v101, v4 ; bin: 66 45 0f d6 55 00
; asm: movq %xmm5, 50(%r14) ; asm: movq %xmm5, 50(%r14)
[-] store.f64 v100, v3+50 ; bin: 66 41 0f d6 6e 32 [-] store.f64 v100, v3+50 ; bin: 66 41 0f d6 6e 32
; asm: movq %xmm10, -50(%rax) ; asm: movq %xmm10, -50(%rax)

2
lib/cretonne/meta/isa/intel/recipes.py
View File

@@ -675,7 +675,7 @@ st_abcd = TailRecipe(
# XX /r register-indirect store of FPR with no offset. # XX /r register-indirect store of FPR with no offset.
fst = TailRecipe( fst = TailRecipe(
'fst', Store, size=1, ins=(FPR, GPR), outs=(), 'fst', Store, size=1, ins=(FPR, GPR_ZERO_DEREF_SAFE), outs=(),
instp=IsEqual(Store.offset, 0), instp=IsEqual(Store.offset, 0),
clobbers_flags=False, clobbers_flags=False,
emit=''' emit='''