Make the fst recipe use the deref-safe register class as well.

2018-02-28 10:12:40 -08:00
parent 9010e576dd
commit ab9298eafa
2 changed files with 11 additions and 1 deletions
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -675,7 +675,7 @@ st_abcd = TailRecipe(

 # XX /r register-indirect store of FPR with no offset.
 fst = TailRecipe(
-        'fst', Store, size=1, ins=(FPR, GPR), outs=(),
+        'fst', Store, size=1, ins=(FPR, GPR_ZERO_DEREF_SAFE), outs=(),
        instp=IsEqual(Store.offset, 0),
        clobbers_flags=False,
        emit='''