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ISLE: Resolve overlaps in the aarch64 backend (#4988)

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Trevor Elliott
2022-09-30 12:57:50 -07:00
committed by GitHub
parent c1d6ca48a7
commit ab4be2bdd1
3 changed files with 239 additions and 237 deletions
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48
cranelift/codegen/src/isa/aarch64/lower_dynamic_neon.isle
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@@ -1,90 +1,90 @@
;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (iadd x y)))
(rule -4 (lower (has_type ty @ (dynamic_lane _ _) (iadd x y)))
(value_reg (add_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (isub x y)))
(rule -5 (lower (has_type ty @ (dynamic_lane _ _) (isub x y)))
(value_reg (sub_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (lane_fits_in_32 ty @ (dynamic_lane _ _)) (imul x y)))
(rule -4 (lower (has_type (lane_fits_in_32 ty @ (dynamic_lane _ _)) (imul x y)))
(value_reg (vec_rrr (VecALUOp.Mul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fadd x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fadd x y)))
(value_reg (vec_rrr (VecALUOp.Fadd) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fsub x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fsub x y)))
(value_reg (vec_rrr (VecALUOp.Fsub) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fmul x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fmul x y)))
(value_reg (vec_rrr (VecALUOp.Fmul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fdiv x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fdiv x y)))
(value_reg (vec_rrr (VecALUOp.Fdiv) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fmin x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fmin x y)))
(value_reg (vec_rrr (VecALUOp.Fmin) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fmax x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fmax x y)))
(value_reg (vec_rrr (VecALUOp.Fmax) (put_in_reg x) (put_in_reg y) (vector_size ty))))
;;;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fmin_pseudo x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fmin_pseudo x y)))
(value_reg (bsl ty
(vec_rrr (VecALUOp.Fcmgt) (put_in_reg x) (put_in_reg y)
(vector_size ty)) (put_in_reg y) (put_in_reg x))))
;;;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty @ (dynamic_lane _ _) (fmax_pseudo x y)))
(rule -2 (lower (has_type ty @ (dynamic_lane _ _) (fmax_pseudo x y)))
(value_reg (bsl ty
(vec_rrr (VecALUOp.Fcmgt) (put_in_reg y) (put_in_reg x)
(vector_size ty)) (put_in_reg y) (put_in_reg x))))
;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_dyn128_int ty) (snarrow x y)))
(rule -2 (lower (has_type (ty_dyn128_int ty) (snarrow x y)))
(if-let _ (zero_value y))
(sqxtn x (lane_size ty)))
(rule (lower (has_type (ty_dyn64_int ty) (snarrow x y)))
(rule -1 (lower (has_type (ty_dyn64_int ty) (snarrow x y)))
(let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
(sqxtn dst (lane_size ty))))
(rule (lower (has_type (ty_dyn128_int ty) (snarrow x y)))
(rule -3 (lower (has_type (ty_dyn128_int ty) (snarrow x y)))
(let ((low_half Reg (sqxtn x (lane_size ty)))
(result Reg (sqxtn2 low_half y (lane_size ty))))
result))
;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_dyn128_int ty) (unarrow x y)))
(rule -2 (lower (has_type (ty_dyn128_int ty) (unarrow x y)))
(if-let _ (zero_value y))
(sqxtun x (lane_size ty)))
(rule (lower (has_type (ty_dyn64_int ty) (unarrow x y)))
(rule -1 (lower (has_type (ty_dyn64_int ty) (unarrow x y)))
(let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
(sqxtun dst (lane_size ty))))
(rule (lower (has_type (ty_dyn128_int ty) (unarrow x y)))
(rule -3 (lower (has_type (ty_dyn128_int ty) (unarrow x y)))
(let ((low_half Reg (sqxtun x (lane_size ty)))
(result Reg (sqxtun2 low_half y (lane_size ty))))
result))
;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type (ty_dyn128_int ty) (uunarrow x y)))
(rule -2 (lower (has_type (ty_dyn128_int ty) (uunarrow x y)))
(if-let _ (zero_value y))
(uqxtn x (lane_size ty)))
(rule (lower (has_type (ty_dyn64_int ty) (uunarrow x y)))
(rule -1 (lower (has_type (ty_dyn64_int ty) (uunarrow x y)))
(let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
(uqxtn dst (lane_size ty))))
(rule (lower (has_type (ty_dyn128_int ty) (uunarrow x y)))
(rule -3 (lower (has_type (ty_dyn128_int ty) (uunarrow x y)))
(let ((low_half Reg (uqxtn x (lane_size ty)))
(result Reg (uqxtn2 low_half y (lane_size ty))))
result))
@@ -101,20 +101,20 @@
;;;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (swiden_low x)))
(rule -1 (lower (has_type ty (swiden_low x)))
(value_reg (vec_extend (VecExtendOp.Sxtl) x $false (lane_size ty))))
;;;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (swiden_high x)))
(rule -1 (lower (has_type ty (swiden_high x)))
(value_reg (vec_extend (VecExtendOp.Sxtl) x $true (lane_size ty))))
;;;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (uwiden_low x)))
(rule -1 (lower (has_type ty (uwiden_low x)))
(value_reg (vec_extend (VecExtendOp.Uxtl) x $false (lane_size ty))))
;;;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type ty (uwiden_high x)))
(rule -1 (lower (has_type ty (uwiden_high x)))
(value_reg (vec_extend (VecExtendOp.Uxtl) x $true (lane_size ty))))