Hook up the handling of tied register constraints.
Tests are forthcoming, we need to implement Intel ABI lowering first.
This commit is contained in:
@@ -155,7 +155,7 @@ impl<'a> Context<'a> {
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pos.goto_top(ebb);
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while let Some(inst) = pos.next_inst() {
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if let Some(constraints) = self.encinfo.operand_constraints(self.encodings[inst]) {
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self.visit_inst(inst, constraints, &mut pos, dfg, tracker);
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self.visit_inst(inst, ebb, constraints, &mut pos, dfg, tracker);
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} else {
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let (_throughs, kills) = tracker.process_ghost(inst);
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self.free_regs(kills);
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@@ -240,6 +240,7 @@ impl<'a> Context<'a> {
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fn visit_inst(&mut self,
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inst: Inst,
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ebb: Ebb,
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constraints: &RecipeConstraints,
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pos: &mut Cursor,
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dfg: &mut DataFlowGraph,
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@@ -248,7 +249,7 @@ impl<'a> Context<'a> {
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// We may need to resolve register constraints if there are any noteworthy uses.
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assert!(self.reg_uses.is_empty());
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self.collect_reg_uses(inst, constraints, dfg);
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self.collect_reg_uses(inst, ebb, constraints, dfg, pos.layout);
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// Calls usually have fixed register uses.
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let call_sig = dfg.call_signature(inst);
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@@ -315,20 +316,23 @@ impl<'a> Context<'a> {
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// operands are always compatible.
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fn collect_reg_uses(&mut self,
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inst: Inst,
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ebb: Ebb,
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constraints: &RecipeConstraints,
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dfg: &DataFlowGraph) {
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dfg: &DataFlowGraph,
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layout: &Layout) {
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let args = dfg.inst_args(inst);
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for (idx, (op, &arg)) in constraints.ins.iter().zip(args).enumerate() {
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let mut reguse = RegUse::new(arg, idx, op.regclass.into());
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let lr = &self.liveness[arg];
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match op.kind {
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ConstraintKind::Stack => continue,
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ConstraintKind::FixedReg(_) => reguse.fixed = true,
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ConstraintKind::Tied(_) => {
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// TODO: If `arg` isn't killed here, we need a copy
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// A tied operand must kill the used value.
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reguse.tied = !lr.killed_at(inst, ebb, layout);
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}
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ConstraintKind::Reg => {}
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}
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let lr = &self.liveness[arg];
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if lr.affinity.is_stack() {
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reguse.spilled = true;
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}
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