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Rename InstructionFormat::IndirectCall for consistency with Opcode::CallIndirect.

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This commit is contained in:
Dan Gohman
2018-04-17 09:43:05 -07:00
parent e2f6705e28
commit a9edb28414
10 changed files with 15 additions and 15 deletions
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2
lib/codegen/meta/base/entities.py
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@@ -20,7 +20,7 @@ stack_slot = EntityRefKind('stack_slot', 'A stack slot.')
global_var = EntityRefKind('global_var', 'A global variable.')
#: A reference to a function sugnature declared in the function preamble.
#: Tbis is used to provide the call signature in an indirect call instruction.
#: This is used to provide the call signature in a call_indirect instruction.
sig_ref = EntityRefKind('sig_ref', 'A function signature.')
#: A reference to an external function declared in the function preamble.

2
lib/codegen/meta/base/formats.py
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@@ -53,7 +53,7 @@ BranchIcmp = InstructionFormat(intcc, VALUE, VALUE, ebb, VARIABLE_ARGS)
BranchTable = InstructionFormat(VALUE, entities.jump_table)
Call = InstructionFormat(func_ref, VARIABLE_ARGS)
IndirectCall = InstructionFormat(sig_ref, VALUE, VARIABLE_ARGS)
CallIndirect = InstructionFormat(sig_ref, VALUE, VARIABLE_ARGS)
FuncAddr = InstructionFormat(func_ref)
Load = InstructionFormat(memflags, VALUE, offset32)

8
lib/codegen/meta/isa/riscv/recipes.py
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@@ -14,7 +14,7 @@ from cdsl.predicates import IsSignedInt
from cdsl.registers import Stack
from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
from base.formats import Unary, UnaryImm, BranchIcmp, Branch, Jump
from base.formats import Call, IndirectCall, RegMove
from base.formats import Call, CallIndirect, RegMove
from .registers import GPR
# The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
@@ -140,11 +140,11 @@ Iret = EncRecipe(
);
''')
# I-type encoding for `jalr` as an indirect call.
# I-type encoding for `jalr` as a call_indirect.
Icall = EncRecipe(
'Icall', IndirectCall, size=4, ins=GPR, outs=(),
'Icall', CallIndirect, size=4, ins=GPR, outs=(),
emit='''
// Indirect instructions are jalr with rd=%x1.
// call_indirect instructions are jalr with rd=%x1.
put_i(
bits,
in_reg0,

4
lib/codegen/meta/isa/x86/recipes.py
View File

@@ -7,7 +7,7 @@ from cdsl.predicates import IsSignedInt, IsEqual, Or
from cdsl.registers import RegClass
from base.formats import Unary, UnaryImm, UnaryBool, Binary, BinaryImm
from base.formats import MultiAry, NullAry
from base.formats import Trap, Call, IndirectCall, Store, Load
from base.formats import Trap, Call, CallIndirect, Store, Load
from base.formats import IntCompare, IntCompareImm, FloatCompare
from base.formats import IntCond, FloatCond
from base.formats import IntSelect, IntCondTrap, FloatCondTrap
@@ -1055,7 +1055,7 @@ call_plt_id = TailRecipe(
''')
call_r = TailRecipe(
'call_r', IndirectCall, size=1, ins=GPR, outs=(),
'call_r', CallIndirect, size=1, ins=GPR, outs=(),
emit='''
PUT_OP(bits, rex1(in_reg0), sink);
modrm_r_bits(in_reg0, bits, sink);