s390x: Add ISLE support

This adds ISLE support for the s390x back-end and moves lowering
of most instructions to ISLE.  The only instructions still remaining
are calls, returns, traps, and branches, most of which will need
additional support in common code.

Generated code is not intended to be (significantly) different
than before; any additional optimizations now made easier to
implement due to the ISLE layer can be added in follow-on patches.

There were a few differences in some filetests, but those are all
just simple register allocation changes (and all to the better!).

cranelift/filetests/filetests/isa/s390x/bitops.clif

@@ -54,8 +54,7 @@ block0(v0: i32):
 
 ; check:  llgfr %r2, %r2
 ; nextln: flogr %r0, %r2
-; nextln: lr %r2, %r0
-; nextln: ahi %r2, -32
+; nextln: ahik %r2, %r0, -32
 ; nextln: br %r14
 
 function %clz_i16(i16) -> i16 {
@@ -66,8 +65,7 @@ block0(v0: i16):
 
 ; check:  llghr %r2, %r2
 ; nextln: flogr %r0, %r2
-; nextln: lr %r2, %r0
-; nextln: ahi %r2, -48
+; nextln: ahik %r2, %r0, -48
 ; nextln: br %r14
 
 function %clz_i8(i8) -> i8 {
@@ -78,8 +76,7 @@ block0(v0: i8):
 
 ; check:  llgcr %r2, %r2
 ; nextln: flogr %r0, %r2
-; nextln: lr %r2, %r0
-; nextln: ahi %r2, -56
+; nextln: ahik %r2, %r0, -56
 ; nextln: br %r14
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -93,7 +90,7 @@ block0(v0: i64):
 }
 
 ; check:  srag %r3, %r2, 63
-; nextln: xgrk %r2, %r3, %r2
+; nextln: xgr %r2, %r3
 ; nextln: flogr %r0, %r2
 ; nextln: lgr %r2, %r0
 ; nextln: br %r14
@@ -106,10 +103,9 @@ block0(v0: i32):
 
 ; check:  lgfr %r2, %r2
 ; nextln: srag %r3, %r2, 63
-; nextln: xgrk %r2, %r3, %r2
+; nextln: xgr %r2, %r3
 ; nextln: flogr %r0, %r2
-; nextln: lr %r2, %r0
-; nextln: ahi %r2, -32
+; nextln: ahik %r2, %r0, -32
 ; nextln: br %r14
 
 function %cls_i16(i16) -> i16 {
@@ -120,10 +116,9 @@ block0(v0: i16):
 
 ; check:  lghr %r2, %r2
 ; nextln: srag %r3, %r2, 63
-; nextln: xgrk %r2, %r3, %r2
+; nextln: xgr %r2, %r3
 ; nextln: flogr %r0, %r2
-; nextln: lr %r2, %r0
-; nextln: ahi %r2, -48
+; nextln: ahik %r2, %r0, -48
 ; nextln: br %r14
 
 function %cls_i8(i8) -> i8 {
@@ -134,10 +129,9 @@ block0(v0: i8):
 
 ; check:  lgbr %r2, %r2
 ; nextln: srag %r3, %r2, 63
-; nextln: xgrk %r2, %r3, %r2
+; nextln: xgr %r2, %r3
 ; nextln: flogr %r0, %r2
-; nextln: lr %r2, %r0
-; nextln: ahi %r2, -56
+; nextln: ahik %r2, %r0, -56
 ; nextln: br %r14
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -151,7 +145,7 @@ block0(v0: i64):
 }
 
 ; check:  lcgr %r3, %r2
-; nextln: ngrk %r2, %r3, %r2
+; nextln: ngr %r2, %r3
 ; nextln: flogr %r0, %r2
 ; nextln: locghie %r0, -1
 ; nextln: lghi %r2, 63
@@ -166,7 +160,7 @@ block0(v0: i32):
 
 ; check:  oihl %r2, 1
 ; nextln: lcgr %r3, %r2
-; nextln: ngrk %r2, %r3, %r2
+; nextln: ngr %r2, %r3
 ; nextln: flogr %r0, %r2
 ; nextln: lhi %r2, 63
 ; nextln: sr %r2, %r0
@@ -180,7 +174,7 @@ block0(v0: i16):
 
 ; check:  oilh %r2, 1
 ; nextln: lcgr %r3, %r2
-; nextln: ngrk %r2, %r3, %r2
+; nextln: ngr %r2, %r3
 ; nextln: flogr %r0, %r2
 ; nextln: lhi %r2, 63
 ; nextln: sr %r2, %r0
@@ -194,7 +188,7 @@ block0(v0: i8):
 
 ; check:  oill %r2, 256
 ; nextln: lcgr %r3, %r2
-; nextln: ngrk %r2, %r3, %r2
+; nextln: ngr %r2, %r3
 ; nextln: flogr %r0, %r2
 ; nextln: lhi %r2, 63
 ; nextln: sr %r2, %r0

cranelift/filetests/filetests/isa/s390x/heap_addr.clif

@@ -13,8 +13,8 @@ block0(v0: i64, v1: i32):
 
 ; check: Block 0:
 ; check:  llgfr %r3, %r3
-; nextln: lg %r4, 0(%r2)
-; nextln: aghi %r4, 0
+; nextln: lghi %r4, 0
+; nextln: ag %r4, 0(%r2)
 ; nextln: clgr %r3, %r4
 ; nextln: jgnh label1 ; jg label2
 ; check: Block 1:

cranelift/filetests/filetests/isa/s390x/shift-rotate.clif

@@ -52,13 +52,12 @@ block0(v0: i16, v1: i16):
 }
 
 ; check:  llhr %r2, %r2
-; nextln: lr %r3, %r4
-; nextln: lcr %r4, %r4
+; nextln: lcr %r4, %r3
 ; nextln: nill %r3, 15
 ; nextln: nill %r4, 15
-; nextln: sllk %r3, %r2, 0(%r3)
-; nextln: srlk %r2, %r2, 0(%r4)
-; nextln: ork %r2, %r3, %r2
+; nextln: sllk %r4, %r2, 0(%r4)
+; nextln: srlk %r2, %r2, 0(%r3)
+; nextln: ork %r2, %r4, %r2
 ; nextln: br %r14
 
 function %rotr_i16_imm(i16) -> i16 {
@@ -81,13 +80,12 @@ block0(v0: i8, v1: i8):
 }
 
 ; check:  llcr %r2, %r2
-; nextln: lr %r3, %r4
-; nextln: lcr %r4, %r4
+; nextln: lcr %r4, %r3
 ; nextln: nill %r3, 7
 ; nextln: nill %r4, 7
-; nextln: sllk %r3, %r2, 0(%r3)
-; nextln: srlk %r2, %r2, 0(%r4)
-; nextln: ork %r2, %r3, %r2
+; nextln: sllk %r4, %r2, 0(%r4)
+; nextln: srlk %r2, %r2, 0(%r3)
+; nextln: ork %r2, %r4, %r2
 ; nextln: br %r14
 
 function %rotr_i8_imm(i8) -> i8 {
@@ -152,10 +150,9 @@ block0(v0: i16, v1: i16):
 }
 
 ; check:  llhr %r2, %r2
-; nextln: lr %r4, %r3
-; nextln: lcr %r3, %r3
-; nextln: nill %r4, 15
+; nextln: lcr %r4, %r3
 ; nextln: nill %r3, 15
+; nextln: nill %r4, 15
 ; nextln: sllk %r3, %r2, 0(%r3)
 ; nextln: srlk %r2, %r2, 0(%r4)
 ; nextln: ork %r2, %r3, %r2
@@ -181,10 +178,9 @@ block0(v0: i8, v1: i8):
 }
 
 ; check:  llcr %r2, %r2
-; nextln: lr %r4, %r3
-; nextln: lcr %r3, %r3
-; nextln: nill %r4, 7
+; nextln: lcr %r4, %r3
 ; nextln: nill %r3, 7
+; nextln: nill %r4, 7
 ; nextln: sllk %r3, %r2, 0(%r3)
 ; nextln: srlk %r2, %r2, 0(%r4)
 ; nextln: ork %r2, %r3, %r2