cranelift: Add ability to auto-update test expectations (#3612)

* cranelift: Add ability to auto-update test expectations

One of the problems of the current `*.clif` testing is that the files
are difficult to update when widespread changes are made (such as
removing modification of the frame pointer). Additionally when changing
register allocation or similar it can cause a large number of changes in
tests but the tests themselves didn't actually break. For this reason
this commit adds the ability to automatically update test expectations.

The idea behind this commit is that tests of the form `test compile` can
also optionally be flagged with the `precise-output` flag:

    test compile precise-output

and when doing so the compiled form of each function is asserted to 100%
match the following comments and their test expectations. If a match is
not found then a `BLESS=1` environment variable can be used to
automatically rewrite the test file itself with the correct assertion.
If the environment variable isn't present and the expectation doesn't
match then the test fails.

It's hoped that, if approved, a follow-up commit can add
`precise-output` to all current `test compile` tests (or make it the
default) and all tests can be mass-updated. When developing locally test
expectations need not be written and instead tests can be run with
`BLESS=1` and the output can be manually verified. The environment
variable will not be present on CI which means that changes to the
output which don't also change the test expectation will cause CI to
fail. Furthermore this should still make updates to the test output
easily readable in review on CI because the test expectations are
intended to look the same as before.

Closes #1539

* Use raw vcode output in tests

* Fix a merge conflict

* Review comments

cranelift/filetests/filetests/isa/aarch64/simd.clif

@@ -1,4 +1,4 @@
-test compile
+test compile precise-output
 set unwind_info=false
 target aarch64
 
@@ -9,10 +9,16 @@ block0:
   return v1
 }
 
-; check:  movz x0, #1
-; nextln:  movk x0, #1, LSL #48
-; nextln:  dup v0.2d, x0
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 4)
+;   Inst 0:   movz x0, #1
+;   Inst 1:   movk x0, #1, LSL #48
+;   Inst 2:   dup v0.2d, x0
+;   Inst 3:   ret
+; }}
 
 function %f2() -> i16x8 {
 block0:
@@ -22,9 +28,15 @@ block0:
   return v2
 }
 
-; check:  movz x0, #42679
-; nextln:  dup v0.8h, w0
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 3)
+;   Inst 0:   movz x0, #42679
+;   Inst 1:   dup v0.8h, w0
+;   Inst 2:   ret
+; }}
 
 function %f3() -> b8x16 {
 block0:
@@ -34,8 +46,14 @@ block0:
   return v2
 }
 
-; check:  movi v0.16b, #255
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 2)
+;   Inst 0:   movi v0.16b, #255
+;   Inst 1:   ret
+; }}
 
 function %f4(i32, i8x16, i8x16) -> i8x16 {
 block0(v0: i32, v1: i8x16, v2: i8x16):
@@ -43,9 +61,15 @@ block0(v0: i32, v1: i8x16, v2: i8x16):
    return v3
 }
 
-; check:  subs wzr, w0, wzr
-; nextln:  vcsel v0.16b, v0.16b, v1.16b, ne (if-then-else diamond)
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 3)
+;   Inst 0:   subs wzr, w0, wzr
+;   Inst 1:   vcsel v0.16b, v0.16b, v1.16b, ne (if-then-else diamond)
+;   Inst 2:   ret
+; }}
 
 function %f5(i64) -> i8x16 {
 block0(v0: i64):
@@ -54,8 +78,14 @@ block0(v0: i64):
   return v2
 }
 
-; check:  ld1r { v0.16b }, [x0]
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 2)
+;   Inst 0:   ld1r { v0.16b }, [x0]
+;   Inst 1:   ret
+; }}
 
 function %f6(i64, i64) -> i8x16, i8x16 {
 block0(v0: i64, v1: i64):
@@ -66,9 +96,15 @@ block0(v0: i64, v1: i64):
   return v4, v5
 }
 
-; check:  ld1r { v0.16b }, [x0]
-; nextln:  ld1r { v1.16b }, [x1]
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 3)
+;   Inst 0:   ld1r { v0.16b }, [x0]
+;   Inst 1:   ld1r { v1.16b }, [x1]
+;   Inst 2:   ret
+; }}
 
 function %f7(i64, i64) -> i8x16, i8x16 {
 block0(v0: i64, v1: i64):
@@ -79,10 +115,16 @@ block0(v0: i64, v1: i64):
   return v4, v5
 }
 
-; check:  ldrb w0, [x0]
-; nextln:  ld1r { v0.16b }, [x1]
-; nextln:  dup v1.16b, w0
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 4)
+;   Inst 0:   ldrb w0, [x0]
+;   Inst 1:   ld1r { v0.16b }, [x1]
+;   Inst 2:   dup v1.16b, w0
+;   Inst 3:   ret
+; }}
 
 function %f8(i64, i64) -> i8x16, i8x16 {
 block0(v0: i64, v1: i64):
@@ -92,10 +134,16 @@ block0(v0: i64, v1: i64):
   return v3, v4
 }
 
-; check:  ldrb w0, [x0]
-; nextln:  dup v0.16b, w0
-; nextln:  dup v1.16b, w0
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 4)
+;   Inst 0:   ldrb w0, [x0]
+;   Inst 1:   dup v0.16b, w0
+;   Inst 2:   dup v1.16b, w0
+;   Inst 3:   ret
+; }}
 
 function %f9() -> i32x2 {
 block0:
@@ -104,9 +152,15 @@ block0:
   return v1
 }
 
-; check:  movi v0.2d, #18374687579166474495
-; nextln:  fmov d0, d0
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 3)
+;   Inst 0:   movi v0.2d, #18374687579166474495
+;   Inst 1:   fmov d0, d0
+;   Inst 2:   ret
+; }}
 
 function %f10() -> i32x4 {
 block0:
@@ -115,8 +169,14 @@ block0:
   return v1
 }
 
-; check:  mvni v0.4s, #15, MSL #16
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 2)
+;   Inst 0:   mvni v0.4s, #15, MSL #16
+;   Inst 1:   ret
+; }}
 
 function %f11() -> f32x4 {
 block0:
@@ -125,5 +185,12 @@ block0:
   return v1
 }
 
-; check:  fmov v0.4s, #1.3125
-; nextln:  ret
+; VCode_ShowWithRRU {{
+;   Entry block: 0
+; Block 0:
+;   (original IR block: block0)
+;   (instruction range: 0 .. 2)
+;   Inst 0:   fmov v0.4s, #1.3125
+;   Inst 1:   ret
+; }}
+