Cranelift AArch64: Avoid invalid encodings for some vector instructions

2021-09-13 11:40:01 +01:00
parent faa117cac4
commit a8aec2e0e6
4 changed files with 205 additions and 20 deletions
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -846,6 +846,7 @@ pub enum Inst {
    },

    /// Zero-extend a SIMD & FP scalar to the full width of a vector register.
+    /// 16-bit scalars require half-precision floating-point support (FEAT_FP16).
    FpuExtend {
        rd: Writable<Reg>,
        rn: Reg,