machinst: make get_output_reg target independent;

This commit is contained in:
Benjamin Bouvier
2020-09-08 15:44:01 +02:00
parent 6a3c4fb54e
commit a835c247c0
4 changed files with 34 additions and 44 deletions

View File

@@ -106,26 +106,6 @@ pub(crate) enum ResultRegImmShift {
ImmShift(ImmShift), ImmShift(ImmShift),
} }
//============================================================================
// Instruction input "slots".
//
// We use these types to refer to operand numbers, and result numbers, together
// with the associated instruction, in a type-safe way.
/// Identifier for a particular input of an instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub(crate) struct InsnInput {
pub(crate) insn: IRInst,
pub(crate) input: usize,
}
/// Identifier for a particular output of an instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub(crate) struct InsnOutput {
pub(crate) insn: IRInst,
pub(crate) output: usize,
}
//============================================================================ //============================================================================
// Lowering: convert instruction inputs to forms that we can use. // Lowering: convert instruction inputs to forms that we can use.
@@ -191,11 +171,6 @@ impl NarrowValueMode {
} }
} }
/// Allocate a register for an instruction output and return it.
pub(crate) fn get_output_reg<C: LowerCtx<I = Inst>>(ctx: &mut C, out: InsnOutput) -> Writable<Reg> {
ctx.get_output(out.insn, out.output)
}
/// Lower an instruction input to a reg. /// Lower an instruction input to a reg.
/// ///
/// The given register will be extended appropriately, according to /// The given register will be extended appropriately, according to

View File

@@ -110,20 +110,6 @@ fn ldst_offset(data: &InstructionData) -> Option<i32> {
} }
} }
/// Identifier for a particular input of an instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
struct InsnInput {
insn: IRInst,
input: usize,
}
/// Identifier for a particular output of an instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
struct InsnOutput {
insn: IRInst,
output: usize,
}
/// Returns whether the given specified `input` is a result produced by an instruction with Opcode /// Returns whether the given specified `input` is a result produced by an instruction with Opcode
/// `op`. /// `op`.
// TODO investigate failures with checking against the result index. // TODO investigate failures with checking against the result index.
@@ -256,10 +242,6 @@ fn input_to_reg_mem_imm(ctx: Ctx, spec: InsnInput) -> RegMemImm {
} }
} }
fn get_output_reg(ctx: Ctx, spec: InsnOutput) -> Writable<Reg> {
ctx.get_output(spec.insn, spec.output)
}
fn emit_cmp(ctx: Ctx, insn: IRInst) { fn emit_cmp(ctx: Ctx, insn: IRInst) {
let ty = ctx.input_ty(insn, 0); let ty = ctx.input_ty(insn, 0);

View File

@@ -1,6 +1,8 @@
//! Miscellaneous helpers for machine backends. //! Miscellaneous helpers for machine backends.
use super::{InsnOutput, LowerCtx, VCodeInst};
use crate::ir::Type; use crate::ir::Type;
use regalloc::{Reg, Writable};
/// Returns the size (in bits) of a given type. /// Returns the size (in bits) of a given type.
pub fn ty_bits(ty: Type) -> usize { pub fn ty_bits(ty: Type) -> usize {
@@ -16,3 +18,11 @@ pub(crate) fn ty_has_int_representation(ty: Type) -> bool {
pub(crate) fn ty_has_float_or_vec_representation(ty: Type) -> bool { pub(crate) fn ty_has_float_or_vec_representation(ty: Type) -> bool {
ty.is_vector() || ty.is_float() ty.is_vector() || ty.is_float()
} }
/// Allocate a register for an instruction output and return it.
pub(crate) fn get_output_reg<I: VCodeInst, C: LowerCtx<I = I>>(
ctx: &mut C,
spec: InsnOutput,
) -> Writable<Reg> {
ctx.get_output(spec.insn, spec.output)
}

View File

@@ -1,6 +1,29 @@
//! A place to park MachInst::Inst fragments which are common across multiple architectures. //! A place to park MachInst::Inst fragments which are common across multiple architectures.
use crate::ir; use crate::ir::{self, Inst as IRInst};
//============================================================================
// Instruction input "slots".
//
// We use these types to refer to operand numbers, and result numbers, together
// with the associated instruction, in a type-safe way.
/// Identifier for a particular input of an instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub(crate) struct InsnInput {
pub(crate) insn: IRInst,
pub(crate) input: usize,
}
/// Identifier for a particular output of an instruction.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub(crate) struct InsnOutput {
pub(crate) insn: IRInst,
pub(crate) output: usize,
}
//============================================================================
// Atomic instructions.
/// Atomic memory update operations. As of 21 Aug 2020 these are used for the aarch64 and x64 /// Atomic memory update operations. As of 21 Aug 2020 these are used for the aarch64 and x64
/// targets. /// targets.