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Add support for 32 bit and 64 bit fcmp for the new backend

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Implements commiss and commisd.
This commit is contained in:
Johnnie Birch
2020-07-10 18:04:16 -07:00
parent fbc05faa49
commit a7cedf3100
5 changed files with 201 additions and 7 deletions
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30
cranelift/codegen/src/isa/x64/inst/emit_tests.rs
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@@ -2711,7 +2711,8 @@ fn test_x64_emit() {
insns.push((Inst::setcc(CC::NLE, w_rsi), "400F9FC6", "setnle %sil"));
insns.push((Inst::setcc(CC::Z, w_r14), "410F94C6", "setz %r14b"));
insns.push((Inst::setcc(CC::LE, w_r14), "410F9EC6", "setle %r14b"));
insns.push((Inst::setcc(CC::P, w_r9), "410F9AC1", "setp %r9b"));
insns.push((Inst::setcc(CC::NP, w_r8), "410F9BC0", "setnp %r8b"));
// ========================================================
// Cmove
insns.push((
@@ -2876,6 +2877,33 @@ fn test_x64_emit() {
"jmp *321(%r10,%rdx,4)",
));
// ========================================================
// XMM_CMP_RM_R
insns.push((
Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, RegMem::reg(xmm1), xmm2),
"0F2ED1",
"ucomiss %xmm1, %xmm2",
));
insns.push((
Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, RegMem::reg(xmm0), xmm9),
"440F2EC8",
"ucomiss %xmm0, %xmm9",
));
insns.push((
Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, RegMem::reg(xmm13), xmm4),
"66410F2EE5",
"ucomisd %xmm13, %xmm4",
));
insns.push((
Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, RegMem::reg(xmm11), xmm12),
"66450F2EE3",
"ucomisd %xmm11, %xmm12",
));
// ========================================================
// XMM_RM_R: float binary ops