AArch64: port misc ops to ISLE. (#4796)
* Add some precise-output compile tests for aarch64. * AArch64: port misc ops to ISLE. - get_pinned_reg / set_pinned_reg - bitcast - stack_addr - extractlane - insertlane - vhigh_bits - iadd_ifcout - fcvt_low_from_sint
This commit is contained in:
Chris Fallin
@@ -2030,3 +2030,212 @@
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;; N.B.: the Ret itself is generated by the ABI.
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(rule (lower (return args))
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(lower_return (range 0 (value_slice_len args)) args))
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;;; Rules for `{get,set}_pinned_reg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (get_pinned_reg))
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(pinned_reg))
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(rule (lower (set_pinned_reg val))
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(side_effect (write_pinned_reg val)))
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;;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type $I32 (bitcast src @ (value_type $F32))))
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(mov_from_vec src 0 (ScalarSize.Size32)))
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(rule (lower (has_type $F32 (bitcast src @ (value_type $I32))))
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(mov_to_fpu src (ScalarSize.Size32)))
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(rule (lower (has_type $I64 (bitcast src @ (value_type $F64))))
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(mov_from_vec src 0 (ScalarSize.Size64)))
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(rule (lower (has_type $F64 (bitcast src @ (value_type $I64))))
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(mov_to_fpu src (ScalarSize.Size64)))
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;;; Rules for `raw_bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (raw_bitcast val))
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val)
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;;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; extractlane with lane 0 can pass through the value unchanged; upper
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;; bits are undefined when a narrower type is in a wider register.
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(rule (lower (has_type (ty_scalar_float _) (extractlane val (u8_from_uimm8 0))))
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val)
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(rule (lower (has_type (ty_int_bool ty)
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(extractlane val
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(u8_from_uimm8 lane))))
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(mov_from_vec val lane (scalar_size ty)))
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(rule (lower (has_type (ty_scalar_float ty)
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(extractlane val @ (value_type vty)
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(u8_from_uimm8 lane))))
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(fpu_move_from_vec val lane (vector_size vty)))
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;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (insertlane vec @ (value_type vty)
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val @ (value_type (ty_int_bool _))
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(u8_from_uimm8 lane)))
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(mov_to_vec vec val lane (vector_size vty)))
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(rule (lower (insertlane vec @ (value_type vty)
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val @ (value_type (ty_scalar_float _))
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(u8_from_uimm8 lane)))
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(mov_vec_elem vec val lane 0 (vector_size vty)))
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;;; Rules for `copy` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (copy x))
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x)
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;;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (stack_addr stack_slot offset))
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(compute_stack_addr stack_slot offset))
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;;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; All three sequences use one integer temporary and two vector
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;; temporaries. The shift is done early so as to give the register
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;; allocator the possibility of using the same reg for `tmp_v1` and
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;; `src_v` in the case that this is the last use of `src_v`. See
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;; https://github.com/WebAssembly/simd/pull/201 for the background and
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;; derivation of these sequences. Alternative sequences are discussed
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;; in https://github.com/bytecodealliance/wasmtime/issues/2296,
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;; although they are not used here.
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(rule (lower (vhigh_bits vec @ (value_type $I8X16)))
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(let (
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;; Replicate the MSB of each of the 16 byte lanes across
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;; the whole lane (sshr is an arithmetic right shift).
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(shifted Reg (vec_shift_imm (VecShiftImmOp.Sshr) 7 vec (VectorSize.Size8x16)))
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;; Bitwise-and with a mask
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;; `0x80402010_08040201_80402010_08040201` to get the bit
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;; in the proper location for each group of 8 lanes.
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(anded Reg (and_vec shifted (constant_f128 0x80402010_08040201_80402010_08040201) (VectorSize.Size8x16)))
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;; Produce a version of `anded` with upper 8 lanes and
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;; lower 8 lanes swapped.
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(anded_swapped Reg (vec_extract anded anded 8))
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;; Zip together the two; with the above this produces the lane permutation:
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;; 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
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(zipped Reg (zip1 anded anded_swapped (VectorSize.Size8x16)))
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;; Add 16-bit lanes together ("add across vector"), so we
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;; get, in the low 16 bits, 15+14+...+8 in the high byte
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;; and 7+6+...+0 in the low byte. This effectively puts
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;; the 16 MSBs together, giving our results.
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;;
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;; N.B.: `Size16x8` is not a typo!
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(result Reg (addv zipped (VectorSize.Size16x8))))
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(mov_from_vec result 0 (ScalarSize.Size16))))
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(rule (lower (vhigh_bits vec @ (value_type $I16X8)))
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(let (
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;; Replicate the MSB of each of the 8 16-bit lanes across
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;; the whole lane (sshr is an arithmetic right shift).
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(shifted Reg (vec_shift_imm (VecShiftImmOp.Sshr) 15 vec (VectorSize.Size16x8)))
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;; Bitwise-and with a mask
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;; `0x0080_0040_0020_0010_0008_0004_0002_0001` to get the
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;; bit in the proper location for each group of 4 lanes.
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(anded Reg (and_vec shifted (constant_f128 0x0080_0040_0020_0010_0008_0004_0002_0001) (VectorSize.Size16x8)))
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;; Add lanes together to get the 8 MSBs in the low byte.
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(result Reg (addv anded (VectorSize.Size16x8))))
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(mov_from_vec result 0 (ScalarSize.Size16))))
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(rule (lower (vhigh_bits vec @ (value_type $I32X4)))
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(let (
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;; Replicate the MSB of each of the 4 32-bit lanes across
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;; the whole lane (sshr is an arithmetic right shift).
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(shifted Reg (vec_shift_imm (VecShiftImmOp.Sshr) 31 vec (VectorSize.Size32x4)))
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;; Bitwise-and with a mask
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;; `0x00000008_00000004_00000002_00000001` to get the bit
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;; in the proper location for each group of 4 lanes.
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(anded Reg (and_vec shifted (constant_f128 0x00000008_00000004_00000002_00000001) (VectorSize.Size32x4)))
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;; Add lanes together to get the 4 MSBs in the low byte.
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(result Reg (addv anded (VectorSize.Size32x4))))
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(mov_from_vec result 0 (ScalarSize.Size32))))
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(rule (lower (vhigh_bits vec @ (value_type $I64X2)))
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(let (
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;; Grab the MSB out of each of the lanes, right-shift to
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;; LSB, and add with a left-shift of upper lane's MSB back
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;; to bit 1. the whole lane (sshr is an arithmetic right
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;; shift).
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(upper_msb Reg (mov_from_vec vec 1 (ScalarSize.Size64)))
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(lower_msb Reg (mov_from_vec vec 0 (ScalarSize.Size64)))
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(upper_msb Reg (lsr_imm $I64 upper_msb (imm_shift_from_u8 63)))
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(lower_msb Reg (lsr_imm $I64 lower_msb (imm_shift_from_u8 63))))
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(add_shift $I64 lower_msb upper_msb (lshl_from_u64 $I64 1))))
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;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; This is a two-output instruction that is needed for the
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;; legalizer's explicit heap-check sequence, among possible other
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;; uses. Its second output is a flags output only ever meant to
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;; check for overflow using the
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;; `backend.unsigned_add_overflow_condition()` condition.
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;;
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;; Note that the CLIF validation will ensure that no flag-setting
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;; operation comes between this IaddIfcout and its use (e.g., a
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;; Trapif). Thus, we can rely on implicit communication through the
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;; processor flags rather than explicitly generating flags into a
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;; register. We simply use the variant of the add instruction that
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;; sets flags (`adds`) here.
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;;
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;; Note that the second output (the flags) need not be generated,
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;; because flags are never materialized into a register; the only
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;; instructions that can use a value of type `iflags` or `fflags`
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;; will look directly for the flags-producing instruction (which can
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;; always be found, by construction) and merge it.
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;;
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;; Now handle the iadd as above, except use an AddS opcode that sets
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;; flags.
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(rule (lower (has_type (ty_int ty)
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(iadd_ifcout a b)))
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(output_pair
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(add_with_flags ty a b)
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(invalid_reg)))
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;;; Rules for `tls_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO.
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;;; Rules for `fcvt_low_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type $F64X2 (fcvt_low_from_sint val)))
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(let ((extended Reg (vec_extend (VecExtendOp.Sxtl) val $false (ScalarSize.Size64)))
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(converted Reg (vec_misc (VecMisc2.Scvtf) extended (VectorSize.Size64x2))))
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converted))
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;;; Rules for `fvpromote_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (fvpromote_low val))
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(vec_rr_long (VecRRLongOp.Fcvtl32) val $false))
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;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO: requires icmp/fcmp first.
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;;; Rules for `selectif` / `selectif_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO: requires icmp/fcmp first.
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;;; Rules for `trueif` / `trueff` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO: requires icmp/fcmp first.
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;;; Rules for `brz`/`brnz`/`brif`/`brff`/`bricmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO: requires icmp/fcmp first.
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;;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO.
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;;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO.
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