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x64: Share a zero in the ushr translation on x64 to free up a register (#5424)

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Share a zero value in the translation of ushr for i128. This increases the lifetime of the value by a few instructions, and reduces the number of registers used in the translation by one, which seems like an acceptable trade-off.
This commit is contained in:
Trevor Elliott
2022-12-12 18:15:43 -08:00
committed by GitHub
parent 9397ea1abe
commit a5ecb5e647
3 changed files with 77 additions and 85 deletions
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7
cranelift/codegen/src/isa/x64/lower.isle
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@@ -521,9 +521,12 @@
(x64_sub $I64
(imm $I64 64)
amt)))
;; Share the zero value to reduce register pressure
(zero Gpr (imm $I64 0))
;; Nullify the carry if we are shifting by a multiple of 128.
(carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64) (RegMemImm.Imm 127) amt)
(cmove $I64 (CC.Z) (imm $I64 0) carry)))
(cmove $I64 (CC.Z) zero carry)))
;; Add the carry bits into the lo.
(lo_shifted_ Gpr (x64_or $I64 carry_ lo_shifted)))
;; Combine the two shifted halves. However, if we are shifting by >= 64
@@ -532,7 +535,7 @@
(with_flags (x64_test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
(consumes_flags_concat
(cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
(cmove $I64 (CC.Z) hi_shifted (imm $I64 0))))))
(cmove $I64 (CC.Z) hi_shifted zero)))))
(rule (lower (has_type $I128 (ushr src amt)))
;; NB: Only the low bits of `amt` matter since we logically mask the shift