Enable SIMD spec tests for f32x4_rounding and f64x4_rounding.

Also address some review comments pointing out minor issues.

build.rs

@@ -212,6 +212,8 @@ fn experimental_x64_should_panic(testsuite: &str, testname: &str, strategy: &str
         ("simd", "simd_splat") => return false,
         ("simd", "simd_store") => return false,
         ("simd", "simd_conversions") => return false,
+        ("simd", "simd_f32x4_rounding") => return false,
+        ("simd", "simd_f64x2_rounding") => return false,
         ("simd", _) => return true,
         _ => {}
     }
@@ -240,18 +242,13 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
             // These are only implemented on aarch64 and x64.
             ("simd", "simd_boolean")
             | ("simd", "simd_f32x4_pmin_pmax")
-            | ("simd", "simd_f64x2_pmin_pmax") => {
+            | ("simd", "simd_f64x2_pmin_pmax")
+            | ("simd", "simd_f32x4_rounding")
+            | ("simd", "simd_f64x2_rounding") => {
                 return !(cfg!(feature = "experimental_x64")
                     || env::var("CARGO_CFG_TARGET_ARCH").unwrap() == "aarch64")
             }
 
-            // These are only implemented on aarch64.
-            ("simd", "simd_f32x4_rounding") | ("simd", "simd_f64x2_rounding") => {
-                return env::var("CARGO_CFG_TARGET_ARCH").unwrap() != "aarch64";
-            }
-
-            // These tests have simd operators which aren't implemented yet.
-            // (currently none)
             _ => {}
         },
         _ => panic!("unrecognized strategy"),

cranelift/codegen/src/isa/x64/inst/args.rs

@@ -1245,6 +1245,11 @@ impl From<FloatCC> for FcmpImm {
 }
 
 /// Encode the rounding modes used as part of the Rounding Control field.
+/// Note, these rounding immediates only consider the rounding control field
+/// (i.e. the rounding mode) which only take up the first two bits when encoded.
+/// However the rounding immediate which this field helps make up, also includes
+/// bits 3 and 4 which define the rounding select and precision mask respectively.
+/// These two bits are not defined here and are implictly set to zero when encoded.
 pub(crate) enum RoundImm {
     RoundNearest = 0x00,
     RoundDown = 0x01,

cranelift/codegen/src/isa/x64/lower.rs

@@ -3240,7 +3240,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                 ctx.emit(Inst::gen_move(dst, src, ty));
                 ctx.emit(Inst::xmm_rm_r_imm(
                     op,
-                    RegMem::reg(dst.to_reg()),
+                    RegMem::from(dst),
                     dst,
                     mode.encode(),
                     false,