Enable SIMD spec tests for f32x4_rounding and f64x4_rounding.

Also address some review comments pointing out minor issues.

cranelift/codegen/src/isa/x64/inst/args.rs

@@ -1245,6 +1245,11 @@ impl From<FloatCC> for FcmpImm {
 }
 
 /// Encode the rounding modes used as part of the Rounding Control field.
+/// Note, these rounding immediates only consider the rounding control field
+/// (i.e. the rounding mode) which only take up the first two bits when encoded.
+/// However the rounding immediate which this field helps make up, also includes
+/// bits 3 and 4 which define the rounding select and precision mask respectively.
+/// These two bits are not defined here and are implictly set to zero when encoded.
 pub(crate) enum RoundImm {
     RoundNearest = 0x00,
     RoundDown = 0x01,

cranelift/codegen/src/isa/x64/lower.rs

@@ -3240,7 +3240,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                 ctx.emit(Inst::gen_move(dst, src, ty));
                 ctx.emit(Inst::xmm_rm_r_imm(
                     op,
-                    RegMem::reg(dst.to_reg()),
+                    RegMem::from(dst),
                     dst,
                     mode.encode(),
                     false,