Add x86 complex encodings for SIMD load-extend instructions

2020-04-30 10:20:59 -07:00
parent 38dff29179
commit a312506262
3 changed files with 127 additions and 2 deletions
--- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
@@ -1354,11 +1354,17 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRIns
        | Opcode::ScalarToVector
        | Opcode::Swizzle
        | Opcode::Uload8x8
+        | Opcode::Uload8x8Complex
        | Opcode::Sload8x8
+        | Opcode::Sload8x8Complex
        | Opcode::Uload16x4
+        | Opcode::Uload16x4Complex
        | Opcode::Sload16x4
+        | Opcode::Sload16x4Complex
        | Opcode::Uload32x2
-        | Opcode::Sload32x2 => {
+        | Opcode::Uload32x2Complex
+        | Opcode::Sload32x2
+        | Opcode::Sload32x2Complex => {
            // TODO
            panic!("Vector ops not implemented.");
        }