Escape backslashes in Python comments.
The latest version of flake8 diagnoses these as invalid escape sequences, so properly escape them.
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@@ -1134,7 +1134,7 @@ srem_imm = Instruction(
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irsub_imm = Instruction(
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irsub_imm = Instruction(
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'irsub_imm', """
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'irsub_imm', """
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Immediate reverse wrapping subtraction: :math:`a := Y - x \pmod{2^B}`.
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Immediate reverse wrapping subtraction: :math:`a := Y - x \\pmod{2^B}`.
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Also works as integer negation when :math:`Y = 0`. Use :inst:`iadd_imm`
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Also works as integer negation when :math:`Y = 0`. Use :inst:`iadd_imm`
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with a negative immediate operand for the reverse immediate
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with a negative immediate operand for the reverse immediate
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@@ -345,7 +345,7 @@ class Instruction(object):
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`(inst, typevars)` pair.
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`(inst, typevars)` pair.
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This version in `Instruction` itself allows non-polymorphic
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This version in `Instruction` itself allows non-polymorphic
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instructions to duck-type as `BoundInstruction`\s.
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instructions to duck-type as `BoundInstruction`\\s.
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"""
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"""
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assert not self.is_polymorphic, self
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assert not self.is_polymorphic, self
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return (self, ())
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return (self, ())
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@@ -98,7 +98,7 @@ def check_concrete_typing_rtl(var_types, rtl):
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Check that a concrete type assignment var_types (Dict[Var, TypeVar]) is
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Check that a concrete type assignment var_types (Dict[Var, TypeVar]) is
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valid for an Rtl rtl. Specifically check that:
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valid for an Rtl rtl. Specifically check that:
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1) For each Var v \in rtl, v is defined in var_types
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1) For each Var v \\in rtl, v is defined in var_types
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2) For all v, var_types[v] is a singleton type
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2) For all v, var_types[v] is a singleton type
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@@ -419,7 +419,7 @@ class TypeEnv(object):
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E.g. if we have a root of the tree that looks like:
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E.g. if we have a root of the tree that looks like:
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typeof_a typeof_b
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typeof_a typeof_b
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\ /
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\\ /
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typeof_x
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typeof_x
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half_width(1)
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half_width(1)
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@@ -430,7 +430,7 @@ class TypeEnv(object):
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resulting graph is:
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resulting graph is:
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typeof_a typeof_b
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typeof_a typeof_b
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\ /
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\\ /
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typeof_x
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typeof_x
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"""
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"""
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source_tvs = set([v.get_typevar() for v in self.vars])
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source_tvs = set([v.get_typevar() for v in self.vars])
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@@ -120,7 +120,7 @@ def legal_bool(bits):
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# type: (int) -> bool
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# type: (int) -> bool
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"""
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"""
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True iff bits is a legal bit width for a bool type.
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True iff bits is a legal bit width for a bool type.
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bits == 1 || bits \in { 8, 16, .. MAX_BITS }
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bits == 1 || bits \\in { 8, 16, .. MAX_BITS }
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"""
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"""
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return bits == 1 or \
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return bits == 1 or \
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(bits >= 8 and bits <= MAX_BITS and is_power_of_two(bits))
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(bits >= 8 and bits <= MAX_BITS and is_power_of_two(bits))
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@@ -113,7 +113,7 @@ class Rtl(object):
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# type: (Rtl) -> None
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# type: (Rtl) -> None
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"""
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"""
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Given that there is only 1 possible concrete typing T for self, assign
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Given that there is only 1 possible concrete typing T for self, assign
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a singleton TV with type t=T[v] for each Var v \in self. Its an error
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a singleton TV with type t=T[v] for each Var v \\in self. Its an error
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to call this on an Rtl with more than 1 possible typing. This modifies
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to call this on an Rtl with more than 1 possible typing. This modifies
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the Rtl in-place.
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the Rtl in-place.
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"""
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"""
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@@ -19,11 +19,11 @@ def verify_semantics(inst, src, xforms):
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Verify that the semantics transforms in xforms correctly describe the
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Verify that the semantics transforms in xforms correctly describe the
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instruction described by the src Rtl. This involves checking that:
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instruction described by the src Rtl. This involves checking that:
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0) src is a single instance of inst
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0) src is a single instance of inst
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1) For all x\in xforms x.src is a single instance of inst
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1) For all x \\in xforms x.src is a single instance of inst
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2) For any concrete values V of Literals in inst:
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2) For any concrete values V of Literals in inst:
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For all concrete typing T of inst:
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For all concrete typing T of inst:
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Exists single x \in xforms that applies to src conretazied to V
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Exists single x \\in xforms that applies to src conretazied to
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and T
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V and T
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"""
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"""
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# 0) The source rtl is always a single instance of inst
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# 0) The source rtl is always a single instance of inst
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assert len(src.rtl) == 1 and src.rtl[0].expr.inst == inst
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assert len(src.rtl) == 1 and src.rtl[0].expr.inst == inst
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