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fuzzgen: Enable s390x and disable unimplemented ops (#5596)

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Also fix assertion failure when using "i128 uext" or "i128 sext"
arguments or return values, as discovered by the fuzzer.
This commit is contained in:
Ulrich Weigand
2023-01-19 19:08:32 +01:00
committed by GitHub
parent 56a981bdd8
commit a2e9a608c1
4 changed files with 44 additions and 5 deletions
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1
cranelift/codegen/src/isa/s390x/abi.rs
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@@ -275,7 +275,6 @@ impl ABIMachineSpec for S390xMachineDeps {
} else if call_conv.extends_wasmtime() {
panic!("i128 args/return values not supported in the Wasmtime ABI");
} else {
assert!(param.extension == ir::ArgumentExtension::None);
// We must pass this by implicit reference.
if args_or_rets == ArgsOrRets::Rets {
// For return values, just force them to memory.

6
cranelift/codegen/src/isa/s390x/inst.isle
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@@ -2975,9 +2975,9 @@
;; Helper to compute the type of an implicitly extended argument/return value.
(decl abi_ext_ty (ArgumentExtension Type) Type)
(rule (abi_ext_ty (ArgumentExtension.None) ty) ty)
(rule (abi_ext_ty (ArgumentExtension.Uext) _) $I64)
(rule (abi_ext_ty (ArgumentExtension.Sext) _) $I64)
(rule 0 (abi_ext_ty _ ty) ty)
(rule 1 (abi_ext_ty (ArgumentExtension.Uext) (gpr32_ty _)) $I64)
(rule 1 (abi_ext_ty (ArgumentExtension.Sext) (gpr32_ty _)) $I64)
;; Helpers for generating immediate values ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

40
cranelift/fuzzgen/src/function_generator.rs
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@@ -502,6 +502,46 @@ fn valid_for_target(triple: &Triple, op: Opcode, args: &[Type], rets: &[Type]) -
)
}
Architecture::S390x => {
exceptions!(
(Opcode::IaddCout),
(Opcode::Udiv, &[I128, I128]),
(Opcode::Sdiv, &[I128, I128]),
(Opcode::Urem, &[I128, I128]),
(Opcode::Srem, &[I128, I128]),
(Opcode::Smin),
(Opcode::Smax),
(Opcode::Umin),
(Opcode::Umax),
(Opcode::Band, &[F32, F32]),
(Opcode::Band, &[F64, F64]),
(Opcode::Bor, &[F32, F32]),
(Opcode::Bor, &[F64, F64]),
(Opcode::Bxor, &[F32, F32]),
(Opcode::Bxor, &[F64, F64]),
(Opcode::Bnot, &[F32, F32]),
(Opcode::Bnot, &[F64, F64]),
(Opcode::BandNot, &[F32, F32]),
(Opcode::BandNot, &[F64, F64]),
(Opcode::BorNot, &[F32, F32]),
(Opcode::BorNot, &[F64, F64]),
(Opcode::BxorNot, &[F32, F32]),
(Opcode::BxorNot, &[F64, F64]),
(Opcode::FcvtToUint, &[F32], &[I128]),
(Opcode::FcvtToUint, &[F64], &[I128]),
(Opcode::FcvtToUintSat, &[F32], &[I128]),
(Opcode::FcvtToUintSat, &[F64], &[I128]),
(Opcode::FcvtToSint, &[F32], &[I128]),
(Opcode::FcvtToSint, &[F64], &[I128]),
(Opcode::FcvtToSintSat, &[F32], &[I128]),
(Opcode::FcvtToSintSat, &[F64], &[I128]),
(Opcode::FcvtFromUint, &[I128], &[F32]),
(Opcode::FcvtFromUint, &[I128], &[F64]),
(Opcode::FcvtFromSint, &[I128], &[F32]),
(Opcode::FcvtFromSint, &[I128], &[F64]),
)
}
Architecture::Riscv64(_) => {
exceptions!(
// TODO

2
fuzz/Cargo.toml
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@@ -10,7 +10,7 @@ cargo-fuzz = true
[dependencies]
anyhow = { workspace = true }
once_cell = { workspace = true }
cranelift-codegen = { workspace = true, features = ["incremental-cache", "x86", "arm64", "riscv64"] }
cranelift-codegen = { workspace = true, features = ["incremental-cache", "x86", "arm64", "s390x", "riscv64"] }
cranelift-reader = { workspace = true }
cranelift-wasm = { workspace = true }
cranelift-filetests = { workspace = true }