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Add encodings for imul instructions to RISC-V.

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This is just the basic 'imul' the M instruction set also has mulh/mulhu which
yield the high bits of a multiplication, and there are div/rem instructions to
be implemented.

These instructions are gated by the use_m predicate, but ISA predicates are not
completely implemented yet.
This commit is contained in:
Jakob Stoklund Olesen
2016-08-30 15:03:32 -07:00
parent c1971db091
commit a1cbeb7f7a
1 changed files with 7 additions and 0 deletions
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7
meta/isa/riscv/encodings.py
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@@ -5,6 +5,7 @@ from __future__ import absolute_import
from cretonne import base
from .defs import RV32, RV64
from .recipes import OPIMM, OPIMM32, OP, OP32, R, Rshamt, I
from .settings import use_m
# Basic arithmetic binary instructions are encoded in an R-type instruction.
for inst, inst_imm, f3, f7 in [
@@ -45,3 +46,9 @@ for inst, inst_imm, f3, f7 in [
RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))
# "M" Standard Extension for Integer Multiplication and Division.
# Gated by the `use_m` flag.
RV32.enc(base.imul.i32, R, OP(0b000, 0b0000001), isap=use_m)
RV64.enc(base.imul.i64, R, OP(0b000, 0b0000001), isap=use_m)
RV64.enc(base.imul.i32, R, OP32(0b000, 0b0000001), isap=use_m)