Switch Cranelift over to regalloc2. (#3989)
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
This commit is contained in:
Chris Fallin
@@ -12,24 +12,19 @@ block0:
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return v2
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 12)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: load_const VCodeConstant(3), %xmm1
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; Inst 3: load_const VCodeConstant(2), %xmm0
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; Inst 4: load_const VCodeConstant(0), %xmm2
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; Inst 5: pshufb %xmm2, %xmm1
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; Inst 6: load_const VCodeConstant(1), %xmm2
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; Inst 7: pshufb %xmm2, %xmm0
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; Inst 8: orps %xmm1, %xmm0
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; Inst 9: movq %rbp, %rsp
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; Inst 10: popq %rbp
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; Inst 11: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; load_const VCodeConstant(3), %xmm1
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; load_const VCodeConstant(2), %xmm0
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; load_const VCodeConstant(0), %xmm9
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; pshufb %xmm1, %xmm1, %xmm9
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; load_const VCodeConstant(1), %xmm12
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; pshufb %xmm0, %xmm0, %xmm12
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; orps %xmm0, %xmm0, %xmm1
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %shuffle_same_ssa_value() -> i8x16 {
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block0:
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@@ -38,20 +33,15 @@ block0:
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return v2
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 8)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: load_const VCodeConstant(1), %xmm0
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; Inst 3: load_const VCodeConstant(0), %xmm1
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; Inst 4: pshufb %xmm1, %xmm0
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; Inst 5: movq %rbp, %rsp
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; Inst 6: popq %rbp
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; Inst 7: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; load_const VCodeConstant(1), %xmm0
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; load_const VCodeConstant(0), %xmm5
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; pshufb %xmm0, %xmm0, %xmm5
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %swizzle() -> i8x16 {
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block0:
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@@ -61,23 +51,17 @@ block0:
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return v2
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 11)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: load_const VCodeConstant(1), %xmm1
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; Inst 3: load_const VCodeConstant(1), %xmm0
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; Inst 4: load_const VCodeConstant(0), %xmm2
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; Inst 5: paddusb %xmm2, %xmm0
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; Inst 6: pshufb %xmm0, %xmm1
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; Inst 7: movdqa %xmm1, %xmm0
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; Inst 8: movq %rbp, %rsp
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; Inst 9: popq %rbp
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; Inst 10: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; load_const VCodeConstant(1), %xmm0
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; load_const VCodeConstant(1), %xmm2
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; load_const VCodeConstant(0), %xmm7
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; paddusb %xmm2, %xmm2, %xmm7
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; pshufb %xmm0, %xmm0, %xmm2
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %splat_i8(i8) -> i8x16 {
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block0(v0: i8):
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@@ -85,21 +69,16 @@ block0(v0: i8):
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return v1
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 9)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: uninit %xmm0
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; Inst 3: pinsrb $0, %rdi, %xmm0
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; Inst 4: pxor %xmm1, %xmm1
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; Inst 5: pshufb %xmm1, %xmm0
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; Inst 6: movq %rbp, %rsp
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; Inst 7: popq %rbp
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; Inst 8: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; uninit %xmm0
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; pinsrb $0, %xmm0, %rdi, %xmm0
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; pxor %xmm6, %xmm6, %xmm6
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; pshufb %xmm0, %xmm0, %xmm6
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %splat_b16() -> b16x8 {
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block0:
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@@ -108,22 +87,17 @@ block0:
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return v1
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 10)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: movl $65535, %esi
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; Inst 3: uninit %xmm0
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; Inst 4: pinsrw $0, %rsi, %xmm0
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; Inst 5: pinsrw $1, %rsi, %xmm0
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; Inst 6: pshufd $0, %xmm0, %xmm0
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; Inst 7: movq %rbp, %rsp
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; Inst 8: popq %rbp
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; Inst 9: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movl $65535, %eax
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; uninit %xmm0
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; pinsrw $0, %xmm0, %rax, %xmm0
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; pinsrw $1, %xmm0, %rax, %xmm0
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; pshufd $0, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %splat_i32(i32) -> i32x4 {
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block0(v0: i32):
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@@ -131,20 +105,15 @@ block0(v0: i32):
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return v1
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 8)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: uninit %xmm0
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; Inst 3: pinsrd $0, %rdi, %xmm0
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; Inst 4: pshufd $0, %xmm0, %xmm0
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; Inst 5: movq %rbp, %rsp
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; Inst 6: popq %rbp
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; Inst 7: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; uninit %xmm0
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; pinsrd $0, %xmm0, %rdi, %xmm0
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; pshufd $0, %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %splat_f64(f64) -> f64x2 {
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block0(v0: f64):
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@@ -152,21 +121,17 @@ block0(v0: f64):
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return v1
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 9)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: uninit %xmm1
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; Inst 3: movsd %xmm0, %xmm1
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; Inst 4: movlhps %xmm0, %xmm1
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; Inst 5: movdqa %xmm1, %xmm0
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; Inst 6: movq %rbp, %rsp
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; Inst 7: popq %rbp
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; Inst 8: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqa %xmm0, %xmm4
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; uninit %xmm0
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; movdqa %xmm4, %xmm5
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; movsd %xmm0, %xmm0, %xmm5
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; movlhps %xmm0, %xmm0, %xmm5
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %load32_zero_coalesced(i64) -> i32x4 {
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block0(v0: i64):
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@@ -175,18 +140,13 @@ block0(v0: i64):
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return v2
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 6)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: movss 0(%rdi), %xmm0
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; Inst 3: movq %rbp, %rsp
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; Inst 4: popq %rbp
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; Inst 5: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movss 0(%rdi), %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %load32_zero_int(i32) -> i32x4 {
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block0(v0: i32):
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@@ -194,18 +154,13 @@ block0(v0: i32):
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return v1
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 6)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: movd %edi, %xmm0
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; Inst 3: movq %rbp, %rsp
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; Inst 4: popq %rbp
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; Inst 5: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movd %edi, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function %load32_zero_float(f32) -> f32x4 {
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block0(v0: f32):
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@@ -213,15 +168,10 @@ block0(v0: f32):
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return v1
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 5)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: movq %rbp, %rsp
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; Inst 3: popq %rbp
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; Inst 4: ret
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; }}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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