Switch Cranelift over to regalloc2. (#3989)

This PR switches Cranelift over to the new register allocator, regalloc2.

See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801)
for a summary of the design changes. This switchover has implications for
core VCode/MachInst types and the lowering pass.

Overall, this change brings improvements to both compile time and speed of
generated code (runtime), as reported in #3942:

```
Benchmark       Compilation (wallclock)     Execution (wallclock)
blake3-scalar   25% faster                  28% faster
blake3-simd     no diff                     no diff
meshoptimizer   19% faster                  17% faster
pulldown-cmark  17% faster                  no diff
bz2             15% faster                  no diff
SpiderMonkey,   21% faster                  2% faster
  fib(30)
clang.wasm      42% faster                  N/A
```

cranelift/filetests/filetests/isa/s390x/jumptable.clif

@@ -1,4 +1,4 @@
-test compile
+test compile precise-output
 target s390x
 
 function %f(i64) -> i64 {
@@ -28,24 +28,32 @@ block5(v5: i64):
   return v6
 }
 
-; check:  clgfi %r2, 3
-; nextln: jghe label1
-; nextln: sllg %r3, %r2, 2
-; nextln: larl %r1, 14 ; agf %r1, 0(%r1, %r3) ; br %r1 ; jt_entries label3 label5 label7
-
-; check:  Block 3
-; check:  lghi %r3, 1
-; nextln: jg
-
-; check:  Block 5
-; check:  lghi %r3, 2
-; nextln: jg
-
-; check:  Block 7
-; check:  lghi %r3, 3
-; nextln: jg
-
-; check:  agr %r2, %r3
-; nextln: br %r14
-
+; block0:
+;   clgfi %r2, 3
+;   jghe label1
+;   sllg %r5, %r2, 2
+;   larl %r1, 14 ; agf %r1, 0(%r1, %r5) ; br %r1 ; jt_entries label3 label5 label7
+; block1:
+;   lghi %r4, 4
+;   jg label2
+; block2:
+;   jg label9
+; block3:
+;   lghi %r4, 1
+;   jg label4
+; block4:
+;   jg label9
+; block5:
+;   lghi %r4, 2
+;   jg label6
+; block6:
+;   jg label9
+; block7:
+;   lghi %r4, 3
+;   jg label8
+; block8:
+;   jg label9
+; block9:
+;   agr %r2, %r4
+;   br %r14