Switch Cranelift over to regalloc2. (#3989)

This PR switches Cranelift over to the new register allocator, regalloc2.

See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801)
for a summary of the design changes. This switchover has implications for
core VCode/MachInst types and the lowering pass.

Overall, this change brings improvements to both compile time and speed of
generated code (runtime), as reported in #3942:

```
Benchmark       Compilation (wallclock)     Execution (wallclock)
blake3-scalar   25% faster                  28% faster
blake3-simd     no diff                     no diff
meshoptimizer   19% faster                  17% faster
pulldown-cmark  17% faster                  no diff
bz2             15% faster                  no diff
SpiderMonkey,   21% faster                  2% faster
  fib(30)
clang.wasm      42% faster                  N/A
```

cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif

@@ -9,16 +9,11 @@ block0:
   return v1
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 4)
-;   Inst 0:   movz x0, #1
-;   Inst 1:   movk x0, #1, LSL #48
-;   Inst 2:   fmov d0, x0
-;   Inst 3:   ret
-; }}
+; block0:
+;   movz x2, #1
+;   movk x2, #1, LSL #48
+;   fmov d0, x2
+;   ret
 
 function %f2() -> i32x4 {
 block0:
@@ -27,13 +22,8 @@ block0:
   return v1
 }
 
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 3)
-;   Inst 0:   movz x0, #42679
-;   Inst 1:   fmov s0, w0
-;   Inst 2:   ret
-; }}
+; block0:
+;   movz x2, #42679
+;   fmov s0, w2
+;   ret