Switch Cranelift over to regalloc2. (#3989)

This PR switches Cranelift over to the new register allocator, regalloc2.

See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801)
for a summary of the design changes. This switchover has implications for
core VCode/MachInst types and the lowering pass.

Overall, this change brings improvements to both compile time and speed of
generated code (runtime), as reported in #3942:

```
Benchmark       Compilation (wallclock)     Execution (wallclock)
blake3-scalar   25% faster                  28% faster
blake3-simd     no diff                     no diff
meshoptimizer   19% faster                  17% faster
pulldown-cmark  17% faster                  no diff
bz2             15% faster                  no diff
SpiderMonkey,   21% faster                  2% faster
  fib(30)
clang.wasm      42% faster                  N/A
```

cranelift/codegen/src/machinst/valueregs.rs

@@ -1,7 +1,9 @@
 //! Data structure for tracking the (possibly multiple) registers that hold one
 //! SSA `Value`.
 
-use regalloc::{RealReg, Reg, VirtualReg, Writable};
+use regalloc2::{PReg, VReg};
+
+use super::{RealReg, Reg, VirtualReg, Writable};
 use std::fmt::Debug;
 
 const VALUE_REGS_PARTS: usize = 2;
@@ -35,17 +37,17 @@ pub trait InvalidSentinel: Copy + Eq {
 }
 impl InvalidSentinel for Reg {
     fn invalid_sentinel() -> Self {
-        Reg::invalid()
+        Reg::from(VReg::invalid())
     }
 }
 impl InvalidSentinel for VirtualReg {
     fn invalid_sentinel() -> Self {
-        VirtualReg::invalid()
+        VirtualReg::from(VReg::invalid())
     }
 }
 impl InvalidSentinel for RealReg {
     fn invalid_sentinel() -> Self {
-        RealReg::invalid()
+        RealReg::from(PReg::invalid())
     }
 }
 impl InvalidSentinel for Writable<Reg> {