Switch Cranelift over to regalloc2. (#3989)
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
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@@ -5,7 +5,6 @@ use crate::ir::{Signature, StackSlot};
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use crate::isa::CallConv;
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use crate::machinst::*;
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use crate::settings;
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use regalloc::{Reg, Set, SpillSlot, Writable};
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use smallvec::SmallVec;
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/// A small vector of instructions (with some reasonable size); appropriate for
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@@ -42,12 +41,6 @@ pub trait ABICallee {
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/// Get the calling convention implemented by this ABI object.
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fn call_conv(&self) -> CallConv;
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/// Get the liveins of the function.
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fn liveins(&self) -> Set<RealReg>;
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/// Get the liveouts of the function.
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fn liveouts(&self) -> Set<RealReg>;
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/// Number of arguments.
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fn num_args(&self) -> usize;
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@@ -106,7 +99,7 @@ pub trait ABICallee {
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fn set_num_spillslots(&mut self, slots: usize);
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/// Update with the clobbered registers, post-regalloc.
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fn set_clobbered(&mut self, clobbered: Set<Writable<RealReg>>);
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fn set_clobbered(&mut self, clobbered: Vec<Writable<RealReg>>);
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/// Get the address of a stackslot.
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fn stackslot_addr(&self, slot: StackSlot, offset: u32, into_reg: Writable<Reg>) -> Self::I;
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