Switch Cranelift over to regalloc2. (#3989)
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
This commit is contained in:
Chris Fallin
@@ -6,8 +6,9 @@ use super::TargetIsa;
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use crate::ir::{condcodes::IntCC, Function};
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#[cfg(feature = "unwind")]
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use crate::isa::unwind::systemv;
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use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings};
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use crate::isa::x64::{inst::regs::create_reg_env_systemv, settings as x64_settings};
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use crate::isa::Builder as IsaBuilder;
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use crate::machinst::Reg;
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use crate::machinst::{
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compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
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};
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@@ -15,8 +16,7 @@ use crate::result::{CodegenError, CodegenResult};
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use crate::settings::{self as shared_settings, Flags};
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use alloc::{boxed::Box, vec::Vec};
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use core::fmt;
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use regalloc::{PrettyPrint, RealRegUniverse, Reg};
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use regalloc2::MachineEnv;
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use target_lexicon::Triple;
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mod abi;
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@@ -30,27 +30,31 @@ pub(crate) struct X64Backend {
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triple: Triple,
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flags: Flags,
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x64_flags: x64_settings::Flags,
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reg_universe: RealRegUniverse,
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reg_env: MachineEnv,
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}
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impl X64Backend {
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/// Create a new X64 backend with the given (shared) flags.
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fn new_with_flags(triple: Triple, flags: Flags, x64_flags: x64_settings::Flags) -> Self {
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let reg_universe = create_reg_universe_systemv(&flags);
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let reg_env = create_reg_env_systemv(&flags);
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Self {
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triple,
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flags,
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x64_flags,
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reg_universe,
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reg_env,
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}
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}
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fn compile_vcode(&self, func: &Function, flags: Flags) -> CodegenResult<VCode<inst::Inst>> {
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fn compile_vcode(
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&self,
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func: &Function,
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flags: Flags,
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) -> CodegenResult<(VCode<inst::Inst>, regalloc2::Output)> {
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// This performs lowering to VCode, register-allocates the code, computes
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// block layout and finalizes branches. The result is ready for binary emission.
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let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone());
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let abi = Box::new(abi::X64ABICallee::new(&func, flags, self.isa_flags())?);
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compile::compile::<Self>(&func, self, abi, &self.reg_universe, emit_info)
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compile::compile::<Self>(&func, self, abi, &self.reg_env, emit_info)
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}
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}
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@@ -61,28 +65,27 @@ impl TargetIsa for X64Backend {
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want_disasm: bool,
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) -> CodegenResult<MachCompileResult> {
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let flags = self.flags();
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let vcode = self.compile_vcode(func, flags.clone())?;
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let (vcode, regalloc_result) = self.compile_vcode(func, flags.clone())?;
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let (buffer, bb_starts, bb_edges) = vcode.emit();
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let buffer = buffer.finish();
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let frame_size = vcode.frame_size();
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let value_labels_ranges = vcode.value_labels_ranges();
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let stackslot_offsets = vcode.stackslot_offsets().clone();
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let want_disasm = want_disasm || log::log_enabled!(log::Level::Debug);
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let emit_result = vcode.emit(®alloc_result, want_disasm, flags.machine_code_cfg_info());
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let frame_size = emit_result.frame_size;
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let value_labels_ranges = emit_result.value_labels_ranges;
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let buffer = emit_result.buffer.finish();
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let stackslot_offsets = emit_result.stackslot_offsets;
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let disasm = if want_disasm {
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Some(vcode.show_rru(Some(&create_reg_universe_systemv(flags))))
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} else {
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None
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};
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if let Some(disasm) = emit_result.disasm.as_ref() {
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log::debug!("disassembly:\n{}", disasm);
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}
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Ok(MachCompileResult {
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buffer,
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frame_size,
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disasm,
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disasm: emit_result.disasm,
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value_labels_ranges,
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stackslot_offsets,
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bb_starts,
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bb_edges,
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bb_starts: emit_result.bb_offsets,
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bb_edges: emit_result.bb_edges,
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})
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}
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@@ -319,30 +322,29 @@ mod test {
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// 00000000 55 push rbp
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// 00000001 4889E5 mov rbp,rsp
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// 00000004 4889FE mov rsi,rdi
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// 00000007 81C634120000 add esi,0x1234
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// 0000000D 85F6 test esi,esi
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// 0000000F 0F841B000000 jz near 0x30
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// 00000015 4889F7 mov rdi,rsi
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// 00000018 4889F0 mov rax,rsi
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// 0000001B 81E834120000 sub eax,0x1234
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// 00000021 01F8 add eax,edi
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// 00000023 85F6 test esi,esi
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// 00000025 0F8505000000 jnz near 0x30
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// 0000002B 4889EC mov rsp,rbp
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// 0000002E 5D pop rbp
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// 0000002F C3 ret
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// 00000030 4889F7 mov rdi,rsi <--- cold block
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// 00000033 81C734120000 add edi,0x1234
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// 00000039 85FF test edi,edi
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// 0000003B 0F85EFFFFFFF jnz near 0x30
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// 00000041 E9D2FFFFFF jmp 0x18
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// 00000004 81C734120000 add edi,0x1234
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// 0000000A 85FF test edi,edi
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// 0000000C 0F841C000000 jz near 0x2e
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// 00000012 4989F8 mov r8,rdi
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// 00000015 4889F8 mov rax,rdi
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// 00000018 81E834120000 sub eax,0x1234
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// 0000001E 4401C0 add eax,r8d
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// 00000021 85FF test edi,edi
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// 00000023 0F8505000000 jnz near 0x2e
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// 00000029 4889EC mov rsp,rbp
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// 0000002C 5D pop rbp
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// 0000002D C3 ret
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// 0000002E 4989F8 mov r8,rdi
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// 00000031 4181C034120000 add r8d,0x1234
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// 00000038 4585C0 test r8d,r8d
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// 0000003B 0F85EDFFFFFF jnz near 0x2e
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// 00000041 E9CFFFFFFF jmp 0x15
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let golden = vec![
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85, 72, 137, 229, 72, 137, 254, 129, 198, 52, 18, 0, 0, 133, 246, 15, 132, 27, 0, 0, 0,
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72, 137, 247, 72, 137, 240, 129, 232, 52, 18, 0, 0, 1, 248, 133, 246, 15, 133, 5, 0, 0,
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0, 72, 137, 236, 93, 195, 72, 137, 247, 129, 199, 52, 18, 0, 0, 133, 255, 15, 133, 239,
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255, 255, 255, 233, 210, 255, 255, 255,
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85, 72, 137, 229, 129, 199, 52, 18, 0, 0, 133, 255, 15, 132, 28, 0, 0, 0, 73, 137, 248,
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72, 137, 248, 129, 232, 52, 18, 0, 0, 68, 1, 192, 133, 255, 15, 133, 5, 0, 0, 0, 72,
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137, 236, 93, 195, 73, 137, 248, 65, 129, 192, 52, 18, 0, 0, 69, 133, 192, 15, 133,
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237, 255, 255, 255, 233, 207, 255, 255, 255,
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];
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assert_eq!(code, &golden[..]);
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