Switch Cranelift over to regalloc2. (#3989)
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
This commit is contained in:
Chris Fallin
@@ -1,26 +1,14 @@
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//! Registers, the Universe thereof, and printing.
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//! Register definitions for regalloc2.
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//!
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//! These are ordered by sequence number, as required in the Universe.
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//! We define 16 GPRs, with indices equal to the hardware encoding,
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//! and 16 XMM registers.
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//!
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//! The caller-saved registers are placed first in order to prefer not to clobber (requiring
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//! saves/restores in prologue/epilogue code) when possible. Note that there is no other heuristic
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//! in the backend that will apply such pressure; the register allocator's cost heuristics are not
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//! aware of the cost of clobber-save/restore code.
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//!
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//! One might worry that this pessimizes code with many callsites, where using caller-saves causes
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//! us to have to save them (as we are the caller) frequently. However, the register allocator
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//! *should be* aware of *this* cost, because it sees that the call instruction modifies all of the
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//! caller-saved (i.e., callee-clobbered) registers.
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//!
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//! Hence, this ordering encodes pressure in one direction (prefer not to clobber registers that we
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//! ourselves have to save) and this is balanaced against the RA's pressure in the other direction
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//! at callsites.
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//! Note also that we make use of pinned VRegs to refer to PRegs.
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use crate::machinst::{AllocationConsumer, RealReg, Reg};
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use crate::settings;
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use alloc::vec::Vec;
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use regalloc::{
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PrettyPrint, RealReg, RealRegUniverse, Reg, RegClass, RegClassInfo, NUM_REG_CLASSES,
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};
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use alloc::string::ToString;
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use regalloc2::{MachineEnv, PReg, RegClass, VReg};
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use std::string::String;
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// Hardware encodings (note the special rax, rcx, rdx, rbx order).
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@@ -42,53 +30,62 @@ pub const ENC_R13: u8 = 13;
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pub const ENC_R14: u8 = 14;
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pub const ENC_R15: u8 = 15;
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fn gpr(enc: u8, index: u8) -> Reg {
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Reg::new_real(RegClass::I64, enc, index)
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// Constructors for Regs.
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fn gpr(enc: u8) -> Reg {
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let preg = PReg::new(enc as usize, RegClass::Int);
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Reg::from(VReg::new(preg.index(), RegClass::Int))
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}
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pub(crate) fn rsi() -> Reg {
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gpr(ENC_RSI, 16)
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gpr(ENC_RSI)
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}
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pub(crate) fn rdi() -> Reg {
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gpr(ENC_RDI, 17)
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gpr(ENC_RDI)
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}
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pub(crate) fn rax() -> Reg {
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gpr(ENC_RAX, 18)
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gpr(ENC_RAX)
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}
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pub(crate) fn rcx() -> Reg {
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gpr(ENC_RCX, 19)
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gpr(ENC_RCX)
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}
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pub(crate) fn rdx() -> Reg {
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gpr(ENC_RDX, 20)
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gpr(ENC_RDX)
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}
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pub(crate) fn r8() -> Reg {
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gpr(ENC_R8, 21)
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gpr(ENC_R8)
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}
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pub(crate) fn r9() -> Reg {
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gpr(ENC_R9, 22)
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gpr(ENC_R9)
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}
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pub(crate) fn r10() -> Reg {
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gpr(ENC_R10, 23)
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gpr(ENC_R10)
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}
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pub(crate) fn r11() -> Reg {
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gpr(ENC_R11, 24)
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gpr(ENC_R11)
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}
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pub(crate) fn r12() -> Reg {
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gpr(ENC_R12, 25)
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gpr(ENC_R12)
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}
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pub(crate) fn r13() -> Reg {
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gpr(ENC_R13, 26)
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gpr(ENC_R13)
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}
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pub(crate) fn r14() -> Reg {
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gpr(ENC_R14, 27)
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gpr(ENC_R14)
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}
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pub(crate) fn rbx() -> Reg {
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gpr(ENC_RBX, 28)
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gpr(ENC_RBX)
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}
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pub(crate) fn r15() -> Reg {
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// r15 is put aside since this is the pinned register.
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gpr(ENC_R15, 29)
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gpr(ENC_R15)
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}
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pub(crate) fn rsp() -> Reg {
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gpr(ENC_RSP)
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}
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pub(crate) fn rbp() -> Reg {
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gpr(ENC_RBP)
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}
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/// The pinned register on this architecture.
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@@ -98,163 +95,177 @@ pub(crate) fn pinned_reg() -> Reg {
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r15()
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}
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fn fpr(enc: u8, index: u8) -> Reg {
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Reg::new_real(RegClass::V128, enc, index)
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fn fpr(enc: u8) -> Reg {
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let preg = PReg::new(enc as usize, RegClass::Float);
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Reg::from(VReg::new(preg.index(), RegClass::Float))
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}
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pub(crate) fn xmm0() -> Reg {
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fpr(0, 0)
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fpr(0)
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}
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pub(crate) fn xmm1() -> Reg {
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fpr(1, 1)
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fpr(1)
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}
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pub(crate) fn xmm2() -> Reg {
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fpr(2, 2)
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fpr(2)
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}
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pub(crate) fn xmm3() -> Reg {
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fpr(3, 3)
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fpr(3)
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}
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pub(crate) fn xmm4() -> Reg {
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fpr(4, 4)
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fpr(4)
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}
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pub(crate) fn xmm5() -> Reg {
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fpr(5, 5)
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fpr(5)
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}
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pub(crate) fn xmm6() -> Reg {
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fpr(6, 6)
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fpr(6)
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}
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pub(crate) fn xmm7() -> Reg {
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fpr(7, 7)
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fpr(7)
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}
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pub(crate) fn xmm8() -> Reg {
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fpr(8, 8)
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fpr(8)
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}
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pub(crate) fn xmm9() -> Reg {
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fpr(9, 9)
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fpr(9)
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}
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pub(crate) fn xmm10() -> Reg {
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fpr(10, 10)
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fpr(10)
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}
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pub(crate) fn xmm11() -> Reg {
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fpr(11, 11)
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fpr(11)
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}
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pub(crate) fn xmm12() -> Reg {
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fpr(12, 12)
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fpr(12)
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}
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pub(crate) fn xmm13() -> Reg {
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fpr(13, 13)
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fpr(13)
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}
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pub(crate) fn xmm14() -> Reg {
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fpr(14, 14)
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fpr(14)
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}
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pub(crate) fn xmm15() -> Reg {
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fpr(15, 15)
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fpr(15)
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}
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pub(crate) fn rsp() -> Reg {
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gpr(ENC_RSP, 30)
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}
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pub(crate) fn rbp() -> Reg {
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gpr(ENC_RBP, 31)
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}
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/// Create the register universe for X64.
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///
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/// The ordering of registers matters, as commented in the file doc comment: assumes the
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/// calling-convention is SystemV, at the moment.
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pub(crate) fn create_reg_universe_systemv(flags: &settings::Flags) -> RealRegUniverse {
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let mut regs = Vec::<(RealReg, String)>::new();
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let mut allocable_by_class = [None; NUM_REG_CLASSES];
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let use_pinned_reg = flags.enable_pinned_reg();
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// XMM registers
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let first_fpr = regs.len();
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regs.push((xmm0().to_real_reg(), "%xmm0".into()));
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regs.push((xmm1().to_real_reg(), "%xmm1".into()));
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regs.push((xmm2().to_real_reg(), "%xmm2".into()));
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regs.push((xmm3().to_real_reg(), "%xmm3".into()));
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regs.push((xmm4().to_real_reg(), "%xmm4".into()));
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regs.push((xmm5().to_real_reg(), "%xmm5".into()));
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regs.push((xmm6().to_real_reg(), "%xmm6".into()));
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regs.push((xmm7().to_real_reg(), "%xmm7".into()));
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regs.push((xmm8().to_real_reg(), "%xmm8".into()));
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regs.push((xmm9().to_real_reg(), "%xmm9".into()));
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regs.push((xmm10().to_real_reg(), "%xmm10".into()));
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regs.push((xmm11().to_real_reg(), "%xmm11".into()));
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regs.push((xmm12().to_real_reg(), "%xmm12".into()));
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regs.push((xmm13().to_real_reg(), "%xmm13".into()));
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regs.push((xmm14().to_real_reg(), "%xmm14".into()));
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regs.push((xmm15().to_real_reg(), "%xmm15".into()));
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let last_fpr = regs.len() - 1;
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// Integer regs.
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let first_gpr = regs.len();
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// Caller-saved, in the SystemV x86_64 ABI.
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regs.push((rsi().to_real_reg(), "%rsi".into()));
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regs.push((rdi().to_real_reg(), "%rdi".into()));
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regs.push((rax().to_real_reg(), "%rax".into()));
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regs.push((rcx().to_real_reg(), "%rcx".into()));
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regs.push((rdx().to_real_reg(), "%rdx".into()));
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regs.push((r8().to_real_reg(), "%r8".into()));
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regs.push((r9().to_real_reg(), "%r9".into()));
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regs.push((r10().to_real_reg(), "%r10".into()));
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regs.push((r11().to_real_reg(), "%r11".into()));
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// Callee-saved, in the SystemV x86_64 ABI.
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regs.push((r12().to_real_reg(), "%r12".into()));
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regs.push((r13().to_real_reg(), "%r13".into()));
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regs.push((r14().to_real_reg(), "%r14".into()));
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regs.push((rbx().to_real_reg(), "%rbx".into()));
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// Other regs, not available to the allocator.
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debug_assert_eq!(r15(), pinned_reg());
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let allocable = if use_pinned_reg {
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// The pinned register is not allocatable in this case, so record the length before adding
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// it.
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let len = regs.len();
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regs.push((r15().to_real_reg(), "%r15/pinned".into()));
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len
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} else {
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regs.push((r15().to_real_reg(), "%r15".into()));
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regs.len()
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};
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let last_gpr = allocable - 1;
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regs.push((rsp().to_real_reg(), "%rsp".into()));
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regs.push((rbp().to_real_reg(), "%rbp".into()));
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allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
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first: first_gpr,
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last: last_gpr,
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suggested_scratch: Some(r12().get_index()),
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});
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allocable_by_class[RegClass::V128.rc_to_usize()] = Some(RegClassInfo {
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first: first_fpr,
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last: last_fpr,
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suggested_scratch: Some(xmm15().get_index()),
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});
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// Sanity-check: the index passed to the Reg ctor must match the order in the register list.
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for (i, reg) in regs.iter().enumerate() {
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assert_eq!(i, reg.0.get_index());
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/// Create the register environment for x64.
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pub(crate) fn create_reg_env_systemv(flags: &settings::Flags) -> MachineEnv {
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fn preg(r: Reg) -> PReg {
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r.to_real_reg().unwrap().into()
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}
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RealRegUniverse {
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regs,
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allocable,
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allocable_by_class,
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let mut env = MachineEnv {
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preferred_regs_by_class: [
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// Preferred GPRs: caller-saved in the SysV ABI.
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vec![
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preg(rsi()),
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preg(rdi()),
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preg(rax()),
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preg(rcx()),
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preg(rdx()),
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preg(r8()),
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preg(r9()),
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// N.B.: not r10; it is our scratch reg.
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preg(r11()),
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],
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// Preferred XMMs: all of them.
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vec![
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preg(xmm0()),
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preg(xmm1()),
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preg(xmm2()),
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preg(xmm3()),
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preg(xmm4()),
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preg(xmm5()),
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preg(xmm6()),
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preg(xmm7()),
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preg(xmm8()),
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preg(xmm9()),
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preg(xmm10()),
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preg(xmm11()),
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preg(xmm12()),
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preg(xmm13()),
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preg(xmm14()),
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// N.B.: not xmm15; it is our scratch reg.
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],
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],
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non_preferred_regs_by_class: [
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// Non-preferred GPRs: callee-saved in the SysV ABI.
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vec![preg(rbx()), preg(r12()), preg(r13()), preg(r14())],
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// Non-preferred XMMs: none.
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vec![],
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],
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scratch_by_class: [preg(r10()), preg(xmm15())],
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fixed_stack_slots: vec![],
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};
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debug_assert_eq!(r15(), pinned_reg());
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if !flags.enable_pinned_reg() {
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env.non_preferred_regs_by_class[0].push(preg(r15()));
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}
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env
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}
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/// Give the name of a RealReg.
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pub fn realreg_name(reg: RealReg) -> &'static str {
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let preg = PReg::from(reg);
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match preg.class() {
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RegClass::Int => match preg.hw_enc() as u8 {
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ENC_RAX => "%rax",
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ENC_RBX => "%rbx",
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ENC_RCX => "%rcx",
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ENC_RDX => "%rdx",
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ENC_RSI => "%rsi",
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ENC_RDI => "%rdi",
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ENC_RBP => "%rbp",
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ENC_RSP => "%rsp",
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ENC_R8 => "%r8",
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ENC_R9 => "%r9",
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ENC_R10 => "%r10",
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ENC_R11 => "%r11",
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ENC_R12 => "%r12",
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ENC_R13 => "%r13",
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ENC_R14 => "%r14",
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ENC_R15 => "%r15",
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_ => panic!("Invalid PReg: {:?}", preg),
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},
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RegClass::Float => match preg.hw_enc() {
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0 => "%xmm0",
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1 => "%xmm1",
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2 => "%xmm2",
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3 => "%xmm3",
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4 => "%xmm4",
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5 => "%xmm5",
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6 => "%xmm6",
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7 => "%xmm7",
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8 => "%xmm8",
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9 => "%xmm9",
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10 => "%xmm10",
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11 => "%xmm11",
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12 => "%xmm12",
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13 => "%xmm13",
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14 => "%xmm14",
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15 => "%xmm15",
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_ => panic!("Invalid PReg: {:?}", preg),
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},
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}
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}
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pub fn show_reg(reg: Reg) -> String {
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if let Some(rreg) = reg.to_real_reg() {
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realreg_name(rreg).to_string()
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} else {
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format!("%{:?}", reg)
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}
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}
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/// If `ireg` denotes an I64-classed reg, make a best-effort attempt to show its name at some
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/// smaller size (4, 2 or 1 bytes).
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pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
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let mut s = reg.show_rru(mb_rru);
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pub fn show_ireg_sized(reg: Reg, size: u8) -> String {
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let mut s = show_reg(reg);
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if reg.get_class() != RegClass::I64 || size == 8 {
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if reg.class() != RegClass::Int || size == 8 {
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// We can't do any better.
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return s;
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}
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@@ -302,3 +313,15 @@ pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: u8) ->
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s
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}
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// N.B.: this is not an `impl PrettyPrint for Reg` because it is
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// specific to x64; other backends have analogous functions. The
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// disambiguation happens statically by virtue of higher-level,
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// x64-specific, types calling the right `pretty_print_reg`. (In other
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// words, we can't pretty-print a `Reg` all by itself in a build that
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// may have multiple backends; but we can pretty-print one as part of
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// an x64 Inst or x64 RegMemImm.)
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pub fn pretty_print_reg(reg: Reg, size: u8, allocs: &mut AllocationConsumer<'_>) -> String {
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let reg = allocs.next(reg);
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show_ireg_sized(reg, size)
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}
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