Switch Cranelift over to regalloc2. (#3989)

This PR switches Cranelift over to the new register allocator, regalloc2.

See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801)
for a summary of the design changes. This switchover has implications for
core VCode/MachInst types and the lowering pass.

Overall, this change brings improvements to both compile time and speed of
generated code (runtime), as reported in #3942:

```
Benchmark       Compilation (wallclock)     Execution (wallclock)
blake3-scalar   25% faster                  28% faster
blake3-simd     no diff                     no diff
meshoptimizer   19% faster                  17% faster
pulldown-cmark  17% faster                  no diff
bz2             15% faster                  no diff
SpiderMonkey,   21% faster                  2% faster
  fib(30)
clang.wasm      42% faster                  N/A
```

cranelift/codegen/src/isa/s390x/inst.isle

@@ -601,7 +601,8 @@
 
     ;; A machine return instruction.
     (Ret
-      (link Reg))
+      (link Reg)
+      (rets VecReg))
 
     ;; A placeholder instruction, generating no code, meaning that a function epilogue must be
     ;; inserted there.
@@ -696,11 +697,10 @@
     (VirtualSPOffsetAdj
       (offset i64))
 
-    ;; A definition of a value label.
-    (ValueLabelMarker
-      (reg Reg)
-      (label ValueLabel))
-
+    ;; Pseudoinstruction to keep a value alive.
+    (DummyUse
+     (reg Reg))
+    
     ;; An unwind pseudoinstruction describing the state of the
     ;; machine at this program point.
     (Unwind