Switch Cranelift over to regalloc2. (#3989)
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
This commit is contained in:
Chris Fallin
@@ -1,7 +1,12 @@
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//! S390x ISA definitions: registers.
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use alloc::string::String;
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use regalloc2::MachineEnv;
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use regalloc2::PReg;
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use regalloc2::VReg;
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use crate::machinst::*;
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use crate::settings;
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use regalloc::{RealRegUniverse, Reg, RegClass, RegClassInfo, Writable, NUM_REG_CLASSES};
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//=============================================================================
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// Registers, the Universe thereof, and printing
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@@ -29,11 +34,8 @@ const FPR_INDICES: [u8; 16] = [
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/// Get a reference to a GPR (integer register).
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pub fn gpr(num: u8) -> Reg {
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assert!(num < 16);
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Reg::new_real(
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RegClass::I64,
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/* enc = */ num,
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/* index = */ GPR_INDICES[num as usize],
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)
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let preg = PReg::new(num as usize, RegClass::Int);
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Reg::from(VReg::new(preg.index(), RegClass::Int))
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}
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/// Get a writable reference to a GPR.
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@@ -44,11 +46,8 @@ pub fn writable_gpr(num: u8) -> Writable<Reg> {
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/// Get a reference to a FPR (floating-point register).
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pub fn fpr(num: u8) -> Reg {
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assert!(num < 16);
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Reg::new_real(
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RegClass::F64,
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/* enc = */ num,
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/* index = */ FPR_INDICES[num as usize],
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)
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let preg = PReg::new(num as usize, RegClass::Float);
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Reg::from(VReg::new(preg.index(), RegClass::Float))
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}
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/// Get a writable reference to a V-register.
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@@ -88,81 +87,73 @@ pub fn zero_reg() -> Reg {
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}
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/// Create the register universe for AArch64.
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pub fn create_reg_universe(_flags: &settings::Flags) -> RealRegUniverse {
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let mut regs = vec![];
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let mut allocable_by_class = [None; NUM_REG_CLASSES];
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// Numbering Scheme: we put FPRs first, then GPRs. The GPRs exclude several registers:
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// r0 (we cannot use this for addressing // FIXME regalloc)
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// r1 (spilltmp)
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// r15 (stack pointer)
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// FPRs.
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let mut base = regs.len();
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regs.push((fpr(0).to_real_reg(), "%f0".into()));
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regs.push((fpr(2).to_real_reg(), "%f2".into()));
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regs.push((fpr(4).to_real_reg(), "%f4".into()));
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regs.push((fpr(6).to_real_reg(), "%f6".into()));
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regs.push((fpr(1).to_real_reg(), "%f1".into()));
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regs.push((fpr(3).to_real_reg(), "%f3".into()));
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regs.push((fpr(5).to_real_reg(), "%f5".into()));
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regs.push((fpr(7).to_real_reg(), "%f7".into()));
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regs.push((fpr(8).to_real_reg(), "%f8".into()));
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regs.push((fpr(10).to_real_reg(), "%f10".into()));
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regs.push((fpr(12).to_real_reg(), "%f12".into()));
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regs.push((fpr(14).to_real_reg(), "%f14".into()));
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regs.push((fpr(9).to_real_reg(), "%f9".into()));
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regs.push((fpr(11).to_real_reg(), "%f11".into()));
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regs.push((fpr(13).to_real_reg(), "%f13".into()));
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regs.push((fpr(15).to_real_reg(), "%f15".into()));
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allocable_by_class[RegClass::F64.rc_to_usize()] = Some(RegClassInfo {
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first: base,
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last: regs.len() - 1,
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suggested_scratch: Some(fpr(1).get_index()),
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});
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// Caller-saved GPRs in the SystemV s390x ABI.
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base = regs.len();
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regs.push((gpr(2).to_real_reg(), "%r2".into()));
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regs.push((gpr(3).to_real_reg(), "%r3".into()));
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regs.push((gpr(4).to_real_reg(), "%r4".into()));
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regs.push((gpr(5).to_real_reg(), "%r5".into()));
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// Callee-saved GPRs in the SystemV s390x ABI.
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// We start from r14 downwards in an attempt to allow the
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// prolog to use as short a STMG as possible.
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regs.push((gpr(14).to_real_reg(), "%r14".into()));
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regs.push((gpr(13).to_real_reg(), "%r13".into()));
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regs.push((gpr(12).to_real_reg(), "%r12".into()));
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regs.push((gpr(11).to_real_reg(), "%r11".into()));
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regs.push((gpr(10).to_real_reg(), "%r10".into()));
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regs.push((gpr(9).to_real_reg(), "%r9".into()));
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regs.push((gpr(8).to_real_reg(), "%r8".into()));
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regs.push((gpr(7).to_real_reg(), "%r7".into()));
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regs.push((gpr(6).to_real_reg(), "%r6".into()));
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allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
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first: base,
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last: regs.len() - 1,
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suggested_scratch: Some(gpr(13).get_index()),
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});
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// Other regs, not available to the allocator.
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let allocable = regs.len();
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regs.push((gpr(15).to_real_reg(), "%r15".into()));
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regs.push((gpr(0).to_real_reg(), "%r0".into()));
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regs.push((gpr(1).to_real_reg(), "%r1".into()));
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// Assert sanity: the indices in the register structs must match their
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// actual indices in the array.
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for (i, reg) in regs.iter().enumerate() {
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assert_eq!(i, reg.0.get_index());
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pub fn create_machine_env(_flags: &settings::Flags) -> MachineEnv {
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fn preg(r: Reg) -> PReg {
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r.to_real_reg().unwrap().into()
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}
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RealRegUniverse {
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regs,
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allocable,
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allocable_by_class,
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MachineEnv {
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preferred_regs_by_class: [
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vec![
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// no r0; can't use for addressing?
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// no r1; it is our spilltmp.
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preg(gpr(2)),
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preg(gpr(3)),
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preg(gpr(4)),
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preg(gpr(5)),
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],
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vec![
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preg(fpr(0)),
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preg(fpr(1)),
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preg(fpr(2)),
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preg(fpr(3)),
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preg(fpr(4)),
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preg(fpr(5)),
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preg(fpr(6)),
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preg(fpr(7)),
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],
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],
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non_preferred_regs_by_class: [
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vec![
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preg(gpr(6)),
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preg(gpr(7)),
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preg(gpr(8)),
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preg(gpr(9)),
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preg(gpr(10)),
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preg(gpr(11)),
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preg(gpr(12)),
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// no r13; it is our scratch reg.
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preg(gpr(14)),
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// no r15; it is the stack pointer.
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],
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vec![
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preg(fpr(8)),
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preg(fpr(9)),
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preg(fpr(10)),
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preg(fpr(11)),
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preg(fpr(12)),
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preg(fpr(13)),
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preg(fpr(14)),
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// no f15; it is our scratch reg.
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],
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],
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scratch_by_class: [preg(gpr(13)), preg(fpr(15))],
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fixed_stack_slots: vec![],
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}
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}
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pub fn show_reg(reg: Reg) -> String {
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if let Some(rreg) = reg.to_real_reg() {
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match rreg.class() {
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RegClass::Int => format!("%r{}", rreg.hw_enc()),
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RegClass::Float => format!("%f{}", rreg.hw_enc()),
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}
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} else {
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format!("%{:?}", reg)
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}
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}
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pub fn pretty_print_reg(reg: Reg, allocs: &mut AllocationConsumer<'_>) -> String {
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let reg = allocs.next(reg);
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show_reg(reg)
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}
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