Switch Cranelift over to regalloc2. (#3989)
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
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@@ -7,21 +7,18 @@
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//!
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//! - Floating-point immediates (FIMM instruction).
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use super::lower_inst;
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use crate::data_value::DataValue;
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use crate::ir::condcodes::{FloatCC, IntCC};
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use crate::ir::types::*;
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use crate::ir::Inst as IRInst;
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use crate::ir::{Opcode, Type, Value};
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::{CodegenError, CodegenResult};
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use crate::isa::aarch64::inst::*;
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use crate::isa::aarch64::AArch64Backend;
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use super::lower_inst;
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use crate::data_value::DataValue;
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use regalloc::{Reg, Writable};
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::machinst::{Reg, Writable};
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use crate::{CodegenError, CodegenResult};
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use smallvec::SmallVec;
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use std::cmp;
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