Add encodings for Intel dynamic shift instructions.

These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".

lib/cretonne/meta/isa/intel/recipes.py

@@ -65,3 +65,6 @@ def OP(op, pp=0, mm=0, rrr=0, w=0):
 
 # XX /r
 Op1rr = EncRecipe('Op1rr', Binary, size=2, ins=(GPR, GPR), outs=0)
+
+# XX /n with one arg in %rcx, for shifts.
+Op1rc = EncRecipe('Op1rc', Binary, size=2, ins=(GPR, GPR.rcx), outs=0)