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Add fixed_nonallocatable constraints when appropriate (#5253)

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Plumb the set of allocatable registers through the OperandCollector and use it validate uses of fixed-nonallocatable registers, like %rsp on x86_64.
This commit is contained in:
Trevor Elliott
2022-11-15 12:49:17 -08:00
committed by GitHub
parent f6ae67f3f0
commit a007e02bd2
13 changed files with 133 additions and 66 deletions
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18
cranelift/codegen/src/isa/riscv64/mod.rs
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@@ -57,12 +57,11 @@ impl Riscv64Backend {
fn compile_vcode(
&self,
func: &Function,
flags: shared_settings::Flags,
) -> CodegenResult<(VCode<inst::Inst>, regalloc2::Output)> {
let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone());
let emit_info = EmitInfo::new(self.flags.clone(), self.isa_flags.clone());
let sigs = SigSet::new::<abi::Riscv64MachineDeps>(func, &self.flags)?;
let abi = abi::Riscv64Callee::new(func, self, &self.isa_flags, &sigs)?;
compile::compile::<Riscv64Backend>(func, flags, self, abi, &self.mach_env, emit_info, sigs)
compile::compile::<Riscv64Backend>(func, self, abi, emit_info, sigs)
}
}
@@ -72,11 +71,14 @@ impl TargetIsa for Riscv64Backend {
func: &Function,
want_disasm: bool,
) -> CodegenResult<CompiledCodeStencil> {
let flags = self.flags();
let (vcode, regalloc_result) = self.compile_vcode(func, flags.clone())?;
let (vcode, regalloc_result) = self.compile_vcode(func)?;
let want_disasm = want_disasm || log::log_enabled!(log::Level::Debug);
let emit_result = vcode.emit(&regalloc_result, want_disasm, flags.machine_code_cfg_info());
let emit_result = vcode.emit(
&regalloc_result,
want_disasm,
self.flags.machine_code_cfg_info(),
);
let frame_size = emit_result.frame_size;
let value_labels_ranges = emit_result.value_labels_ranges;
let buffer = emit_result.buffer.finish();
@@ -115,6 +117,10 @@ impl TargetIsa for Riscv64Backend {
&self.flags
}
fn machine_env(&self) -> &MachineEnv {
&self.mach_env
}
fn isa_flags(&self) -> Vec<shared_settings::Value> {
self.isa_flags.iter().collect()
}