From 9fcd56122044428e6fa2d3941b459ad4ef47cc6d Mon Sep 17 00:00:00 2001 From: bjorn3 Date: Sun, 22 Dec 2019 07:10:36 +0100 Subject: [PATCH] Use explicit rex for brz and brnz encodings (#1308) Fixes #1305. This papers over the problem to prevent crashes while we investigate the cause. --- cranelift/codegen/meta/src/isa/x86/encodings.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs index 4fe2232508..68cc77be0e 100644 --- a/cranelift/codegen/meta/src/isa/x86/encodings.rs +++ b/cranelift/codegen/meta/src/isa/x86/encodings.rs @@ -1368,10 +1368,10 @@ pub(crate) fn define( e.enc_both(brff, rec_brfd.opcodes(&JUMP_NEAR_IF_OVERFLOW)); // Note that the tjccd opcode will be prefixed with 0x0f. - e.enc_i32_i64(brz, rec_tjccb.opcodes(&JUMP_SHORT_IF_EQUAL)); - e.enc_i32_i64(brz, rec_tjccd.opcodes(&TEST_BYTE_REG)); - e.enc_i32_i64(brnz, rec_tjccb.opcodes(&JUMP_SHORT_IF_NOT_EQUAL)); - e.enc_i32_i64(brnz, rec_tjccd.opcodes(&TEST_REG)); + e.enc_i32_i64_explicit_rex(brz, rec_tjccb.opcodes(&JUMP_SHORT_IF_EQUAL)); + e.enc_i32_i64_explicit_rex(brz, rec_tjccd.opcodes(&TEST_BYTE_REG)); + e.enc_i32_i64_explicit_rex(brnz, rec_tjccb.opcodes(&JUMP_SHORT_IF_NOT_EQUAL)); + e.enc_i32_i64_explicit_rex(brnz, rec_tjccd.opcodes(&TEST_REG)); // Branch on a b1 value in a register only looks at the low 8 bits. See also // bint encodings below.