diff --git a/cranelift/filetests/wasm/conversions.cton b/cranelift/filetests/wasm/conversions.cton
new file mode 100644
index 0000000000..459e20e3bf
--- /dev/null
+++ b/cranelift/filetests/wasm/conversions.cton
@@ -0,0 +1,11 @@
+; Test code generation for WebAssembly type conversion operators.
+test compile
+
+set is_64bit=1
+isa intel haswell
+
+function %i32_wrap_i64(i64) -> i32 {
+ebb0(v0: i64):
+    v1 = ireduce.i32 v0
+    return v1
+}
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 6b04ae110d..db039f36a1 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -193,3 +193,8 @@ I64.enc(base.bint.i64.b1, *r.urm.rex(0x0f, 0xb6, w=1))
 I64.enc(base.bint.i64.b1, *r.urm_abcd(0x0f, 0xb6))  # zext to i64 implicit.
 I64.enc(base.bint.i32.b1, *r.urm.rex(0x0f, 0xb6))
 I64.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
+
+# Numerical conversions.
+
+# Converting i64 to i32 is a no-op in 64-bit mode.
+I64.enc(base.ireduce.i32.i64, r.null, 0)
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 8ae65f4723..5ff1e8b225 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -190,6 +190,10 @@ class TailRecipe:
         return (self.recipes[name], bits)
 
 
+# A null unary instruction that takes a GPR register. Can be used for identity
+# copies and no-op conversions.
+null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
+
 # XX /r
 rr = TailRecipe(
         'rr', Binary, size=1, ins=(GPR, GPR), outs=0,