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Rename CallConv::Native to CallConv::SystemV. (#291)

Browse Source 
To keep cross-compiling straightforward, Cretonne shouldn't have any
behavior that depends on the host. This renames the "Native" calling
convention to "SystemV", which has a defined meaning for each target,
so that it's clear that the calling convention doesn't change
depending on what host Cretonne is running on.
This commit is contained in:
Dan Gohman
2018-03-30 12:32:14 -07:00
committed by GitHub
parent 6606b88136
commit 9e4ab7dc86
44 changed files with 157 additions and 156 deletions
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2
cranelift/docs/callex.cton
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@@ -1,6 +1,6 @@
test verifier
function %gcd(i32 uext, i32 uext) -> i32 uext native {
function %gcd(i32 uext, i32 uext) -> i32 uext system_v {
fn1 = function %divmod(i32 uext, i32 uext) -> i32 uext, i32 uext
ebb1(v1: i32, v2: i32):

2
cranelift/docs/example.cton
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@@ -1,6 +1,6 @@
test verifier
function %average(i32, i32) -> f32 native {
function %average(i32, i32) -> f32 system_v {
ss1 = explicit_slot 8 ; Stack slot for ``sum``.
ebb1(v1: i32, v2: i32):

6
cranelift/docs/langref.rst
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@@ -400,11 +400,11 @@ convention:
param : type [paramext] [paramspecial]
paramext : "uext" | "sext"
paramspecial : "sret" | "link" | "fp" | "csr" | "vmctx"
callconv : "native" | "spiderwasm"
callconv : "system_v" | "spiderwasm"
Parameters and return values have flags whose meaning is mostly target
dependent. They make it possible to call native functions on the target
platform. When calling other Cretonne functions, the flags are not necessary.
dependent. These flags support interfacing with code produced by other
compilers.
Functions that are called directly must be declared in the :term:`function
preamble`:

2
cranelift/filetests/domtree/loops.cton
View File

@@ -59,7 +59,7 @@ function %test(i32) {
; nextln: ebb5:
; nextln: }
function %loop2(i32) native {
function %loop2(i32) system_v {
ebb0(v0: i32):
brz v0, ebb1 ; dominates: ebb1 ebb3 ebb4 ebb5
jump ebb2 ; dominates: ebb2

2
cranelift/filetests/domtree/loops2.cton
View File

@@ -43,7 +43,7 @@ function %loop1(i32) {
; nextln: ebb9:
; nextln: }
function %loop2(i32) native {
function %loop2(i32) system_v {
ebb0(v0: i32):
brz v0, ebb1 ; dominates: ebb1 ebb3 ebb4 ebb5
jump ebb2 ; dominates: ebb2

2
cranelift/filetests/isa/intel/abi-bool.cton
View File

@@ -2,7 +2,7 @@ test compile
set is_64bit=1
isa intel haswell
function %foo(i64, i64, i64, i32) -> b1 native {
function %foo(i64, i64, i64, i32) -> b1 system_v {
ebb3(v0: i64, v1: i64, v2: i64, v3: i32):
v5 = icmp ne v2, v2
v8 = iconst.i64 0

12
cranelift/filetests/isa/intel/abi32.cton
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@@ -5,14 +5,14 @@ isa intel
; regex: V=v\d+
function %f() {
sig0 = (i32) -> i32 native
; check: sig0 = (i32 [0]) -> i32 [%rax] native
sig0 = (i32) -> i32 system_v
; check: sig0 = (i32 [0]) -> i32 [%rax] system_v
sig1 = (i64) -> b1 native
; check: sig1 = (i32 [0], i32 [4]) -> b1 [%rax] native
sig1 = (i64) -> b1 system_v
; check: sig1 = (i32 [0], i32 [4]) -> b1 [%rax] system_v
sig2 = (f32, i64) -> f64 native
; check: sig2 = (f32 [0], i32 [4], i32 [8]) -> f64 [%xmm0] native
sig2 = (f32, i64) -> f64 system_v
; check: sig2 = (f32 [0], i32 [4], i32 [8]) -> f64 [%xmm0] system_v
ebb0:
return

12
cranelift/filetests/isa/intel/abi64.cton
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@@ -6,14 +6,14 @@ isa intel
; regex: V=v\d+
function %f() {
sig0 = (i32) -> i32 native
; check: sig0 = (i32 [%rdi]) -> i32 [%rax] native
sig0 = (i32) -> i32 system_v
; check: sig0 = (i32 [%rdi]) -> i32 [%rax] system_v
sig1 = (i64) -> b1 native
; check: sig1 = (i64 [%rdi]) -> b1 [%rax] native
sig1 = (i64) -> b1 system_v
; check: sig1 = (i64 [%rdi]) -> b1 [%rax] system_v
sig2 = (f32, i64) -> f64 native
; check: sig2 = (f32 [%xmm0], i64 [%rdi]) -> f64 [%xmm0] native
sig2 = (f32, i64) -> f64 system_v
; check: sig2 = (f32 [%xmm0], i64 [%rdi]) -> f64 [%xmm0] system_v
ebb0:
return

4
cranelift/filetests/isa/intel/legalize-libcall.cton
View File

@@ -9,7 +9,7 @@ ebb0(v0: f32):
v1 = floor v0
return v1
}
; check: function %floor(f32 [%xmm0]) -> f32 [%xmm0] native {
; check: sig0 = (f32) -> f32 native
; check: function %floor(f32 [%xmm0]) -> f32 [%xmm0] system_v {
; check: sig0 = (f32) -> f32 system_v
; check: fn0 = sig0 %FloorF32
; check: v1 = call fn0(v0)

2
cranelift/filetests/isa/intel/prologue-epilogue.cton
View File

@@ -9,7 +9,7 @@ ebb0:
return
}
; check: function %foo(i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15]) -> i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15] native {
; check: function %foo(i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15]) -> i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15] system_v {
; nextln: ss0 = explicit_slot 168, offset -224
; nextln: ss1 = incoming_arg 56, offset -56
; check: ebb0(v0: i64 [%rbp], v1: i64 [%rbx], v2: i64 [%r12], v3: i64 [%r13], v4: i64 [%r14], v5: i64 [%r15]):

4
cranelift/filetests/isa/riscv/abi-e.cton
View File

@@ -7,8 +7,8 @@ isa riscv enable_e
function %f() {
; Spilling into the stack args after %x15 since %16 and up are not
; available in RV32E.
sig0 = (i64, i64, i64, i64) -> i64 native
; check: sig0 = (i32 [%x10], i32 [%x11], i32 [%x12], i32 [%x13], i32 [%x14], i32 [%x15], i32 [0], i32 [4]) -> i32 [%x10], i32 [%x11] native
sig0 = (i64, i64, i64, i64) -> i64 system_v
; check: sig0 = (i32 [%x10], i32 [%x11], i32 [%x12], i32 [%x13], i32 [%x14], i32 [%x15], i32 [0], i32 [4]) -> i32 [%x10], i32 [%x11] system_v
ebb0:
return
}

24
cranelift/filetests/isa/riscv/abi.cton
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@@ -5,27 +5,27 @@ isa riscv
; regex: V=v\d+
function %f() {
sig0 = (i32) -> i32 native
; check: sig0 = (i32 [%x10]) -> i32 [%x10] native
sig0 = (i32) -> i32 system_v
; check: sig0 = (i32 [%x10]) -> i32 [%x10] system_v
sig1 = (i64) -> b1 native
; check: sig1 = (i32 [%x10], i32 [%x11]) -> b1 [%x10] native
sig1 = (i64) -> b1 system_v
; check: sig1 = (i32 [%x10], i32 [%x11]) -> b1 [%x10] system_v
; The i64 argument must go in an even-odd register pair.
sig2 = (f32, i64) -> f64 native
; check: sig2 = (f32 [%f10], i32 [%x12], i32 [%x13]) -> f64 [%f10] native
sig2 = (f32, i64) -> f64 system_v
; check: sig2 = (f32 [%f10], i32 [%x12], i32 [%x13]) -> f64 [%f10] system_v
; Spilling into the stack args.
sig3 = (f64, f64, f64, f64, f64, f64, f64, i64) -> f64 native
; check: sig3 = (f64 [%f10], f64 [%f11], f64 [%f12], f64 [%f13], f64 [%f14], f64 [%f15], f64 [%f16], i32 [0], i32 [4]) -> f64 [%f10] native
sig3 = (f64, f64, f64, f64, f64, f64, f64, i64) -> f64 system_v
; check: sig3 = (f64 [%f10], f64 [%f11], f64 [%f12], f64 [%f13], f64 [%f14], f64 [%f15], f64 [%f16], i32 [0], i32 [4]) -> f64 [%f10] system_v
; Splitting vectors.
sig4 = (i32x4) native
; check: sig4 = (i32 [%x10], i32 [%x11], i32 [%x12], i32 [%x13]) native
sig4 = (i32x4) system_v
; check: sig4 = (i32 [%x10], i32 [%x11], i32 [%x12], i32 [%x13]) system_v
; Splitting vectors, then splitting ints.
sig5 = (i64x4) native
; check: sig5 = (i32 [%x10], i32 [%x11], i32 [%x12], i32 [%x13], i32 [%x14], i32 [%x15], i32 [%x16], i32 [%x17]) native
sig5 = (i64x4) system_v
; check: sig5 = (i32 [%x10], i32 [%x11], i32 [%x12], i32 [%x13], i32 [%x14], i32 [%x15], i32 [%x16], i32 [%x17]) system_v
ebb0:
return

4
cranelift/filetests/isa/riscv/legalize-abi.cton
View File

@@ -106,7 +106,7 @@ ebb0(v0: i64x4):
}
function %indirect(i32) {
sig1 = () native
sig1 = () system_v
ebb0(v0: i32):
call_indirect sig1, v0()
return
@@ -114,7 +114,7 @@ ebb0(v0: i32):
; The first argument to call_indirect doesn't get altered.
function %indirect_arg(i32, f32x2) {
sig1 = (f32x2) native
sig1 = (f32x2) system_v
ebb0(v0: i32, v1: f32x2):
call_indirect sig1, v0(v1)
; check: call_indirect sig1, v0($V, $V)

30
cranelift/filetests/isa/riscv/parse-encoding.cton
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@@ -3,32 +3,32 @@ test legalizer
isa riscv
function %parse_encoding(i32 [%x5]) -> i32 [%x10] {
; check: function %parse_encoding(i32 [%x5], i32 link [%x1]) -> i32 [%x10], i32 link [%x1] native {
; check: function %parse_encoding(i32 [%x5], i32 link [%x1]) -> i32 [%x10], i32 link [%x1] system_v {
sig0 = (i32 [%x10]) -> i32 [%x10] native
; check: sig0 = (i32 [%x10]) -> i32 [%x10] native
sig0 = (i32 [%x10]) -> i32 [%x10] system_v
; check: sig0 = (i32 [%x10]) -> i32 [%x10] system_v
sig1 = (i32 [%x10], i32 [%x11]) -> b1 [%x10] native
; check: sig1 = (i32 [%x10], i32 [%x11]) -> b1 [%x10] native
sig1 = (i32 [%x10], i32 [%x11]) -> b1 [%x10] system_v
; check: sig1 = (i32 [%x10], i32 [%x11]) -> b1 [%x10] system_v
sig2 = (f32 [%f10], i32 [%x12], i32 [%x13]) -> f64 [%f10] native
; check: sig2 = (f32 [%f10], i32 [%x12], i32 [%x13]) -> f64 [%f10] native
sig2 = (f32 [%f10], i32 [%x12], i32 [%x13]) -> f64 [%f10] system_v
; check: sig2 = (f32 [%f10], i32 [%x12], i32 [%x13]) -> f64 [%f10] system_v
; Arguments on stack where not necessary
sig3 = (f64 [%f10], i32 [0], i32 [4]) -> f64 [%f10] native
; check: sig3 = (f64 [%f10], i32 [0], i32 [4]) -> f64 [%f10] native
sig3 = (f64 [%f10], i32 [0], i32 [4]) -> f64 [%f10] system_v
; check: sig3 = (f64 [%f10], i32 [0], i32 [4]) -> f64 [%f10] system_v
; Stack argument before register argument
sig4 = (f32 [72], i32 [%x10]) native
; check: sig4 = (f32 [72], i32 [%x10]) native
sig4 = (f32 [72], i32 [%x10]) system_v
; check: sig4 = (f32 [72], i32 [%x10]) system_v
; Return value on stack
sig5 = () -> f32 [0] native
; check: sig5 = () -> f32 [0] native
sig5 = () -> f32 [0] system_v
; check: sig5 = () -> f32 [0] system_v
; function + signature
fn0 = function %bar(i32 [%x10]) -> b1 [%x10] native
; check: sig6 = (i32 [%x10]) -> b1 [%x10] native
fn0 = function %bar(i32 [%x10]) -> b1 [%x10] system_v
; check: sig6 = (i32 [%x10]) -> b1 [%x10] system_v
; nextln: fn0 = sig6 %bar
ebb0(v0: i32):

2
cranelift/filetests/licm/complex.cton
View File

@@ -1,6 +1,6 @@
test licm
function %complex(i32) -> i32 native {
function %complex(i32) -> i32 system_v {
ebb0(v0: i32):
jump ebb1(v0)

12
cranelift/filetests/parser/branch.cton
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@@ -9,7 +9,7 @@ ebb0:
ebb1:
jump ebb0()
}
; sameln: function %minimal() native {
; sameln: function %minimal() system_v {
; nextln: ebb0:
; nextln: jump ebb1
; nextln:
@@ -25,7 +25,7 @@ ebb0(v90: i32):
ebb1(v91: i32):
jump ebb0(v91)
}
; sameln: function %onearg(i32) native {
; sameln: function %onearg(i32) system_v {
; nextln: ebb0(v90: i32):
; nextln: jump ebb1(v90)
; nextln:
@@ -41,7 +41,7 @@ ebb0(v90: i32, v91: f32):
ebb1(v92: i32, v93: f32):
jump ebb0(v92, v93)
}
; sameln: function %twoargs(i32, f32) native {
; sameln: function %twoargs(i32, f32) system_v {
; nextln: ebb0(v90: i32, v91: f32):
; nextln: jump ebb1(v90, v91)
; nextln:
@@ -57,7 +57,7 @@ ebb0(v90: i32):
ebb1:
brnz v90, ebb1()
}
; sameln: function %minimal(i32) native {
; sameln: function %minimal(i32) system_v {
; nextln: ebb0(v90: i32):
; nextln: brz v90, ebb1
; nextln:
@@ -72,7 +72,7 @@ ebb0(v90: i32, v91: f32):
ebb1(v92: i32, v93: f32):
brnz v90, ebb0(v92, v93)
}
; sameln: function %twoargs(i32, f32) native {
; sameln: function %twoargs(i32, f32) system_v {
; nextln: ebb0(v90: i32, v91: f32):
; nextln: brz v90, ebb1(v90, v91)
; nextln:
@@ -94,7 +94,7 @@ ebb30:
ebb40:
trap user4
}
; sameln: function %jumptable(i32) native {
; sameln: function %jumptable(i32) system_v {
; check: jt2 = jump_table 0, 0, ebb10, ebb40, ebb20, ebb30
; check: jt200 = jump_table 0
; check: ebb10(v3: i32):

10
cranelift/filetests/parser/call.cton
View File

@@ -5,7 +5,7 @@ function %mini() {
ebb1:
return
}
; sameln: function %mini() native {
; sameln: function %mini() system_v {
; nextln: ebb1:
; nextln: return
; nextln: }
@@ -29,10 +29,10 @@ function %signatures() {
fn5 = sig11 %foo
fn8 = function %bar(i32) -> b1
}
; sameln: function %signatures() native {
; check: sig10 = () native
; sameln: function %signatures() system_v {
; check: sig10 = () system_v
; check: sig11 = (i32, f64) -> i32, b1 spiderwasm
; check: sig12 = (i32) -> b1 native
; check: sig12 = (i32) -> b1 system_v
; not: fn0
; check: fn5 = sig11 %foo
; check: fn8 = sig12 %bar
@@ -88,7 +88,7 @@ function %special1(i32 sret, i32 fp, i32 csr, i32 link) -> i32 link, i32 fp, i32
ebb0(v1: i32, v2: i32, v3: i32, v4: i32):
return v4, v2, v3, v1
}
; check: function %special1(i32 sret, i32 fp, i32 csr, i32 link) -> i32 link, i32 fp, i32 csr, i32 sret native {
; check: function %special1(i32 sret, i32 fp, i32 csr, i32 link) -> i32 link, i32 fp, i32 csr, i32 sret system_v {
; check: ebb0(v1: i32, v2: i32, v3: i32, v4: i32):
; check: return v4, v2, v3, v1
; check: }

2
cranelift/filetests/parser/instruction_encoding.cton
View File

@@ -13,7 +13,7 @@ ebb1(v0: i32 [%x8], v1: i32):
@55 v9 = iadd v8, v7
@a5 [Iret#5] return v0, v8
}
; sameln: function %foo(i32, i32) native {
; sameln: function %foo(i32, i32) system_v {
; nextln: ebb1(v0: i32 [%x8], v1: i32):
; nextln: [-,-]$WS v2 = iadd v0, v1
; nextln: [-]$WS trap heap_oob

2
cranelift/filetests/parser/keywords.cton
View File

@@ -2,4 +2,4 @@ test cat
; 'function' is not a keyword, and can be used as the name of a function too.
function %function() {}
; check: function %function() native
; check: function %function() system_v

4
cranelift/filetests/parser/rewrite.cton
View File

@@ -9,7 +9,7 @@ ebb100(v20: i32):
v9200 = f64const 0x4.0p0
trap user4
}
; sameln: function %defs() native {
; sameln: function %defs() system_v {
; nextln: ebb100(v20: i32):
; nextln: v1000 = iconst.i32x8 5
; nextln: v9200 = f64const 0x1.0000000000000p2
@@ -23,7 +23,7 @@ ebb100(v20: i32):
v200 = iadd v20, v1000
jump ebb100(v1000)
}
; sameln: function %use_value() native {
; sameln: function %use_value() system_v {
; nextln: ebb100(v20: i32):
; nextln: v1000 = iadd_imm v20, 5
; nextln: v200 = iadd v20, v1000

28
cranelift/filetests/parser/tiny.cton
View File

@@ -5,7 +5,7 @@ function %minimal() {
ebb0:
trap user0
}
; sameln: function %minimal() native {
; sameln: function %minimal() system_v {
; nextln: ebb0:
; nextln: trap user0
; nextln: }
@@ -18,7 +18,7 @@ ebb0:
v1 = iconst.i8 6
v2 = ishl v0, v1
}
; sameln: function %ivalues() native {
; sameln: function %ivalues() system_v {
; nextln: ebb0:
; nextln: v0 = iconst.i32 2
; nextln: v1 = iconst.i8 6
@@ -34,7 +34,7 @@ ebb0:
v2 = bextend.b32 v1
v3 = bxor v0, v2
}
; sameln: function %bvalues() native {
; sameln: function %bvalues() system_v {
; nextln: ebb0:
; nextln: v0 = bconst.b32 true
; nextln: v1 = bconst.b8 false
@@ -47,17 +47,17 @@ function %select() {
ebb0(v90: i32, v91: i32, v92: b1):
v0 = select v92, v90, v91
}
; sameln: function %select() native {
; sameln: function %select() system_v {
; nextln: ebb0(v90: i32, v91: i32, v92: b1):
; nextln: v0 = select v92, v90, v91
; nextln: }
; Polymorphic instruction controlled by third operand.
function %selectif() native {
function %selectif() system_v {
ebb0(v95: i32, v96: i32, v97: b1):
v98 = selectif.i32 eq v97, v95, v96
}
; sameln: function %selectif() native {
; sameln: function %selectif() system_v {
; nextln: ebb0(v95: i32, v96: i32, v97: b1):
; nextln: v98 = selectif.i32 eq v97, v95, v96
; nextln: }
@@ -69,7 +69,7 @@ ebb0:
v1 = extractlane v0, 3
v2 = insertlane v0, 1, v1
}
; sameln: function %lanes() native {
; sameln: function %lanes() system_v {
; nextln: ebb0:
; nextln: v0 = iconst.i32x4 2
; nextln: v1 = extractlane v0, 3
@@ -85,7 +85,7 @@ ebb0(v90: i32, v91: i32):
v3 = irsub_imm v91, 45
br_icmp eq v90, v91, ebb0(v91, v90)
}
; sameln: function %icmp(i32, i32) native {
; sameln: function %icmp(i32, i32) system_v {
; nextln: ebb0(v90: i32, v91: i32):
; nextln: v0 = icmp eq v90, v91
; nextln: v1 = icmp ult v90, v91
@@ -101,7 +101,7 @@ ebb0(v90: f32, v91: f32):
v1 = fcmp uno v90, v91
v2 = fcmp lt v90, v91
}
; sameln: function %fcmp(f32, f32) native {
; sameln: function %fcmp(f32, f32) system_v {
; nextln: ebb0(v90: f32, v91: f32):
; nextln: v0 = fcmp eq v90, v91
; nextln: v1 = fcmp uno v90, v91
@@ -115,7 +115,7 @@ ebb0(v90: i32, v91: f32):
v0 = bitcast.i8x4 v90
v1 = bitcast.i32 v91
}
; sameln: function %bitcast(i32, f32) native {
; sameln: function %bitcast(i32, f32) system_v {
; nextln: ebb0(v90: i32, v91: f32):
; nextln: v0 = bitcast.i8x4 v90
; nextln: v1 = bitcast.i32 v91
@@ -135,7 +135,7 @@ ebb0:
stack_store v1, ss10+2
stack_store v2, ss2
}
; sameln: function %stack() native {
; sameln: function %stack() system_v {
; check: ss2 = explicit_slot 4
; check: ss3 = incoming_arg 4, offset 8
; check: ss4 = outgoing_arg 4
@@ -162,7 +162,7 @@ ebb0(v1: i32):
store aligned v3, v1+12
store notrap aligned v3, v1-12
}
; sameln: function %memory(i32) native {
; sameln: function %memory(i32) system_v {
; nextln: ebb0(v1: i32):
; nextln: v2 = load.i64 v1
; nextln: v3 = load.i64 aligned v1
@@ -187,7 +187,7 @@ ebb0(v1: i32):
regfill v1, ss0 -> %10
return
}
; sameln: function %diversion(i32) native {
; sameln: function %diversion(i32) system_v {
; nextln: ss0 = spill_slot 4
; check: ebb0(v1: i32):
; nextln: regmove v1, %10 -> %20
@@ -204,7 +204,7 @@ ebb0:
copy_special %20 -> %10
return
}
; sameln: function %copy_special() native {
; sameln: function %copy_special() system_v {
; nextln: ebb0:
; nextln: copy_special %10 -> %20
; nextln: copy_special %20 -> %10

2
cranelift/filetests/regalloc/coalesce.cton
View File

@@ -109,7 +109,7 @@ ebb1(v10: i32):
return v11
}
function %gvn_unremovable_phi(i32) native {
function %gvn_unremovable_phi(i32) system_v {
ebb0(v0: i32):
v2 = iconst.i32 0
jump ebb2(v2, v0)

12
cranelift/filetests/regalloc/coalescing-207.cton
View File

@@ -5,12 +5,12 @@ isa intel haswell
; Reported as https://github.com/Cretonne/cretonne/issues/207
;
; The coalescer creates a virtual register with two interfering values.
function %pr207(i64 vmctx, i32, i32) -> i32 native {
function %pr207(i64 vmctx, i32, i32) -> i32 system_v {
gv0 = vmctx-8
heap0 = static gv0, min 0, bound 0x5000, guard 0x0040_0000
sig0 = (i64 vmctx, i32, i32) -> i32 native
sig1 = (i64 vmctx, i32, i32, i32) -> i32 native
sig2 = (i64 vmctx, i32, i32, i32) -> i32 native
sig0 = (i64 vmctx, i32, i32) -> i32 system_v
sig1 = (i64 vmctx, i32, i32, i32) -> i32 system_v
sig2 = (i64 vmctx, i32, i32, i32) -> i32 system_v
fn0 = sig0 u0:2
fn1 = sig1 u0:0
fn2 = sig2 u0:1
@@ -1034,10 +1034,10 @@ ebb92(v767: i32):
}
; Same problem from musl.wasm.
function %musl(f64 [%xmm0], i64 vmctx [%rdi]) -> f64 [%xmm0] native {
function %musl(f64 [%xmm0], i64 vmctx [%rdi]) -> f64 [%xmm0] system_v {
gv0 = vmctx
heap0 = static gv0, min 0, bound 0x0001_0000_0000, guard 0x8000_0000
sig0 = (f64 [%xmm0], i32 [%rdi], i64 vmctx [%rsi]) -> f64 [%xmm0] native
sig0 = (f64 [%xmm0], i32 [%rdi], i64 vmctx [%rsi]) -> f64 [%xmm0] system_v
fn0 = sig0 u0:517
ebb0(v0: f64, v1: i64):

2
cranelift/filetests/regalloc/coalescing-216.cton
View File

@@ -5,7 +5,7 @@ isa intel haswell
; Reported as https://github.com/Cretonne/cretonne/issues/216 from the Binaryen fuzzer.
;
; The (old) coalescer creates a virtual register with two identical values.
function %pr216(i32 [%rdi], i64 vmctx [%rsi]) -> i64 [%rax] native {
function %pr216(i32 [%rdi], i64 vmctx [%rsi]) -> i64 [%rax] system_v {
ebb0(v0: i32, v1: i64):
v3 = iconst.i64 0
v5 = iconst.i32 0

2
cranelift/filetests/regalloc/coloring-227.cton
View File

@@ -2,7 +2,7 @@ test regalloc
set is_64bit
isa intel haswell
function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) native {
function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
gv0 = vmctx
heap0 = static gv0, min 0, bound 0x0001_0000_0000, guard 0x8000_0000

2
cranelift/filetests/regalloc/ghost-param.cton
View File

@@ -9,7 +9,7 @@ isa intel haswell
;
; Test case by binaryen fuzzer!
function %pr215(i64 vmctx [%rdi]) native {
function %pr215(i64 vmctx [%rdi]) system_v {
ebb0(v0: i64):
v10 = iconst.i64 0
v1 = bitcast.f64 v10

2
cranelift/filetests/regalloc/global-fixed.cton
View File

@@ -2,7 +2,7 @@ test regalloc
set is_64bit=1
isa intel haswell
function %foo() native {
function %foo() system_v {
ebb4:
v3 = iconst.i32 0
jump ebb3

2
cranelift/filetests/regalloc/intel-regres.cton
View File

@@ -11,7 +11,7 @@ isa intel
; This ended up confusong the constraint solver which had not made a record of
; the fixed register assignment for v9 since it was already in the correct
; register.
function %pr147(i32) -> i32 native {
function %pr147(i32) -> i32 system_v {
ebb0(v0: i32):
v1 = iconst.i32 0
v2 = iconst.i32 1

2
cranelift/filetests/regalloc/output-interference.cton
View File

@@ -2,7 +2,7 @@ test regalloc
set is_64bit=1
isa intel haswell
function %test(i64) -> i64 native {
function %test(i64) -> i64 system_v {
ebb0(v0: i64):
v2 = iconst.i64 12
; This division clobbers two of its fixed input registers on Intel.

6
cranelift/filetests/regalloc/reload-208.cton
View File

@@ -11,11 +11,11 @@ isa intel haswell
;
; The problem was the reload pass rewriting EBB arguments on "brnz v9, ebb3(v9)"
function %pr208(i64 vmctx [%rdi]) native {
function %pr208(i64 vmctx [%rdi]) system_v {
gv0 = vmctx-8
heap0 = static gv0, min 0, bound 0x5000, guard 0x0040_0000
sig0 = (i64 vmctx [%rdi]) -> i32 [%rax] native
sig1 = (i64 vmctx [%rdi], i32 [%rsi]) native
sig0 = (i64 vmctx [%rdi]) -> i32 [%rax] system_v
sig1 = (i64 vmctx [%rdi], i32 [%rsi]) system_v
fn0 = sig0 u0:1
fn1 = sig1 u0:3

2
cranelift/filetests/regalloc/reload.cton
View File

@@ -5,7 +5,7 @@ isa riscv enable_e
; Check that we can handle a function return value that got spilled.
function %spill_return() -> i32 {
fn0 = function %foo() -> i32 native
fn0 = function %foo() -> i32 system_v
ebb0:
v0 = call fn0()

4
cranelift/filetests/regalloc/schedule-moves.cton
View File

@@ -1,7 +1,7 @@
test regalloc
isa intel haswell
function %pr165() native {
function %pr165() system_v {
ebb0:
v0 = iconst.i32 0x0102_0304
v1 = iconst.i32 0x1102_0304
@@ -19,7 +19,7 @@ ebb0:
; Same as above, but use so many registers that spilling is required.
; Note: This is also a candidate for using xchg instructions.
function %emergency_spill() native {
function %emergency_spill() system_v {
ebb0:
v0 = iconst.i32 0x0102_0304
v1 = iconst.i32 0x1102_0304

2
cranelift/filetests/regalloc/spill-noregs.cton
View File

@@ -13,7 +13,7 @@ isa intel
;
; The spiller was not releasing register pressure for dead EBB parameters.
function %pr223(i32 [%rdi], i64 vmctx [%rsi]) -> i64 [%rax] native {
function %pr223(i32 [%rdi], i64 vmctx [%rsi]) -> i64 [%rax] system_v {
ebb0(v0: i32, v1: i64):
v2 = iconst.i32 0
v3 = iconst.i64 0

4
cranelift/filetests/regalloc/spill.cton
View File

@@ -93,7 +93,7 @@ ebb0(v0: i32):
; The same value used as indirect callee and argument.
function %doubleuse_icall1(i32) {
sig0 = (i32) native
sig0 = (i32) system_v
ebb0(v0: i32):
; not:copy
call_indirect sig0, v0(v0)
@@ -102,7 +102,7 @@ ebb0(v0: i32):
; The same value used as indirect callee and two arguments.
function %doubleuse_icall2(i32) {
sig0 = (i32, i32) native
sig0 = (i32, i32) system_v
ebb0(v0: i32):
; check: $(c=$V) = copy v0
call_indirect sig0, v0(v0, v0)

4
cranelift/filetests/verifier/defs_dominates_uses.cton
View File

@@ -2,14 +2,14 @@ test verifier
; Test verification that uses properly dominate defs.
function %non_dominating(i32) -> i32 native {
function %non_dominating(i32) -> i32 system_v {
ebb0(v0: i32):
v1 = iadd.i32 v2, v0 ; error: uses value from non-dominating
v2 = iadd.i32 v1, v0
return v2
}
function %inst_uses_its_own_values(i32) -> i32 native {
function %inst_uses_its_own_values(i32) -> i32 system_v {
ebb0(v0: i32):
v1 = iadd.i32 v1, v0 ; error: uses value from itself
return v1