Update examples to reflect that Cretonne indices typically start at 0.

cranelift/docs/callex.cton

@@ -1,13 +1,13 @@
 test verifier
 
 function %gcd(i32 uext, i32 uext) -> i32 uext system_v {
-    fn1 = %divmod(i32 uext, i32 uext) -> i32 uext, i32 uext
+    fn0 = %divmod(i32 uext, i32 uext) -> i32 uext, i32 uext
 
-ebb1(v1: i32, v2: i32):
+ebb1(v0: i32, v1: i32):
-    brz v2, ebb2
+    brz v1, ebb2
-    v3, v4 = call fn1(v1, v2)
+    v2, v3 = call fn0(v0, v1)
-    return v3
+    return v2
 
 ebb2:
-    return v1
+    return v0
 }

cranelift/docs/cton_domain.py

@@ -6,7 +6,7 @@
 #
 # .. cton::type:: type
 #     Document an IR type.
-# .. cton:inst:: v1, v2 = inst op1, op2
+# .. cton:inst:: v0, v1 = inst op0, op1
 #     Document an IR instruction.
 #
 from __future__ import absolute_import
@@ -146,9 +146,9 @@ class CtonInst(CtonObject):
     def handle_signature(self, sig, signode):
         # Look for signatures like
         #
-        #   v1, v2 = foo op1, op2
+        #   v0, v1 = foo op0, op1
-        #   v1 = foo
+        #   v0 = foo
-        #   foo op1
+        #   foo op0
 
         parts = re.split(sep_equal, sig, 1)
         if len(parts) == 2:

cranelift/docs/example.cton

@@ -1,31 +1,31 @@
 test verifier
 
 function %average(i32, i32) -> f32 system_v {
-    ss1 = explicit_slot 8         ; Stack slot for ``sum``.
+    ss0 = explicit_slot 8         ; Stack slot for ``sum``.
 
-ebb1(v1: i32, v2: i32):
+ebb1(v0: i32, v1: i32):
-    v3 = f64const 0x0.0
+    v2 = f64const 0x0.0
-    stack_store v3, ss1
+    stack_store v2, ss0
-    brz v2, ebb3                  ; Handle count == 0.
+    brz v1, ebb3                  ; Handle count == 0.
-    v4 = iconst.i32 0
+    v3 = iconst.i32 0
-    jump ebb2(v4)
+    jump ebb2(v3)
 
-ebb2(v5: i32):
+ebb2(v4: i32):
-    v6 = imul_imm v5, 4
+    v5 = imul_imm v4, 4
-    v7 = iadd v1, v6
+    v6 = iadd v0, v5
-    v8 = load.f32 v7              ; array[i]
+    v7 = load.f32 v6              ; array[i]
-    v9 = fpromote.f64 v8
+    v8 = fpromote.f64 v7
-    v10 = stack_load.f64 ss1
+    v9 = stack_load.f64 ss0
-    v11 = fadd v9, v10
+    v10 = fadd v8, v9
-    stack_store v11, ss1
+    stack_store v10, ss0
-    v12 = iadd_imm v5, 1
+    v11 = iadd_imm v4, 1
-    v13 = icmp ult v12, v2
+    v12 = icmp ult v11, v1
-    brnz v13, ebb2(v12)           ; Loop backedge.
+    brnz v12, ebb2(v11)           ; Loop backedge.
-    v14 = stack_load.f64 ss1
+    v13 = stack_load.f64 ss0
-    v15 = fcvt_from_uint.f64 v2
+    v14 = fcvt_from_uint.f64 v1
-    v16 = fdiv v14, v15
+    v15 = fdiv v13, v14
-    v17 = fdemote.f32 v16
+    v16 = fdemote.f32 v15
-    return v17
+    return v16
 
 ebb3:
     v100 = f32const +NaN

cranelift/docs/langref.rst

@@ -37,7 +37,7 @@ The first line of a function definition provides the function *name* and
 the :term:`function signature` which declares the parameter and return types.
 Then follows the :term:`function preamble` which declares a number of entities
 that can be referenced inside the function. In the example above, the preamble
-declares a single explicit stack slot, ``ss1``.
+declares a single explicit stack slot, ``ss0``.
 
 After the preamble follows the :term:`function body` which consists of
 :term:`extended basic block`\s (EBBs), the first of which is the
@@ -533,10 +533,10 @@ in :ref:`unrestricted loads and stores <memory>`.
 The :inst:`stack_addr` instruction can be used to macro-expand the stack access
 instructions before instruction selection::
 
-    v1 = stack_load.f64 ss3, 16
+    v0 = stack_load.f64 ss3, 16
     ; Expands to:
-    v9 = stack_addr ss3, 16
+    v1 = stack_addr ss3, 16
-    v1 = load.f64 v9
+    v0 = load.f64 v1
 
 When Cretonne code is running in a sandbox, it can also be necessary to include
 stack overflow checks in the prologue.

cranelift/docs/testing.rst

@@ -226,13 +226,13 @@ command::
     ; regex: I=\binst\d+\b
     ; check: label="{ebb0 | <$(BRZ=$I)>brz ebb2 | <$(JUMP=$I)>jump ebb1}"]
 
-    ebb0(v1: i32, v2: i32):
+    ebb0(v0: i32, v1: i32):
-        brz v2, ebb2            ; unordered: ebb0:$BRZ -> ebb2
+        brz v1, ebb2            ; unordered: ebb0:$BRZ -> ebb2
-        v4 = iconst.i32 0
+        v2 = iconst.i32 0
-        jump ebb1(v4)           ; unordered: ebb0:$JUMP -> ebb1
+        jump ebb1(v2)           ; unordered: ebb0:$JUMP -> ebb1
 
     ebb1(v5: i32):
-        return v1
+        return v0
 
     ebb2:
         v100 = f32const 0.0
@@ -303,10 +303,10 @@ that instruction is compared to the directive::
 
     function %int32() {
     ebb0:
-        [-,%x5]             v1 = iconst.i32 1
+        [-,%x5]             v0 = iconst.i32 1
-        [-,%x6]             v2 = iconst.i32 2
+        [-,%x6]             v1 = iconst.i32 2
-        [R#0c,%x7]          v10 = iadd v1, v2       ; bin: 006283b3
+        [R#0c,%x7]          v10 = iadd v0, v1       ; bin: 006283b3
-        [R#200c,%x8]        v11 = isub v1, v2       ; bin: 40628433
+        [R#200c,%x8]        v11 = isub v0, v1       ; bin: 40628433
         return
     }