Address review comments
- put the division in the synthetic instruction as well, - put the branch table check in the inst's emission code, - replace OneWayCondJmp by TrapIf vcode instruction, - add comments describing code generated by the synthetic instructions
This commit is contained in:
Benjamin Bouvier
@@ -57,12 +57,15 @@ pub enum Inst {
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loc: SourceLoc,
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},
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/// A synthetic sequence to implement the right inline checks for signed remainder and modulo,
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/// A synthetic sequence to implement the right inline checks for remainder and division,
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/// assuming the dividend is in $rax.
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/// Puts the result back into $rax if is_div, $rdx if !is_div, to mimic what the div
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/// instruction does.
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SignedDivOrRem {
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/// The generated code sequence is described in the emit's function match arm for this
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/// instruction.
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CheckedDivOrRemSeq {
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is_div: bool,
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is_signed: bool,
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size: u8,
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divisor: Reg,
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loc: SourceLoc,
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@@ -224,15 +227,14 @@ pub enum Inst {
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not_taken: BranchTarget,
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},
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/// A one-way conditional branch, invisible to the CFG processing; used *only* as part of
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/// straight-line sequences in code to be emitted.
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OneWayJmpCond { cc: CC, dst: BranchTarget },
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/// Jump-table sequence, as one compound instruction (see note in lower.rs for rationale).
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JmpTable {
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/// The generated code sequence is described in the emit's function match arm for this
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/// instruction.
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JmpTableSeq {
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idx: Reg,
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tmp1: Writable<Reg>,
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tmp2: Writable<Reg>,
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default_target: BranchTarget,
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targets: Vec<BranchTarget>,
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targets_for_term: Vec<MachLabel>,
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},
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@@ -240,6 +242,13 @@ pub enum Inst {
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/// Indirect jump: jmpq (reg mem).
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JmpUnknown { target: RegMem },
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/// Traps if the condition code is set.
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TrapIf {
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cc: CC,
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trap_code: TrapCode,
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srcloc: SourceLoc,
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},
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/// A debug trap.
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Hlt,
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@@ -411,14 +420,6 @@ impl Inst {
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trap_info: (srcloc, trap_code),
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}
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}
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/// Returns the size of a trap instruction, which must be fixed. Asserted during codegen.
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pub(crate) fn size_of_trap() -> u32 {
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2
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}
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pub(crate) fn one_way_jmp(cc: CC, dst: BranchTarget) -> Inst {
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Inst::OneWayJmpCond { cc, dst }
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}
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pub(crate) fn setcc(cc: CC, dst: Writable<Reg>) -> Inst {
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debug_assert!(dst.to_reg().get_class() == RegClass::I64);
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@@ -494,6 +495,14 @@ impl Inst {
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pub(crate) fn jmp_unknown(target: RegMem) -> Inst {
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Inst::JmpUnknown { target }
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}
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pub(crate) fn trap_if(cc: CC, trap_code: TrapCode, srcloc: SourceLoc) -> Inst {
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Inst::TrapIf {
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cc,
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trap_code,
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srcloc,
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}
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}
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}
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//=============================================================================
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@@ -564,13 +573,15 @@ impl ShowWithRRU for Inst {
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}),
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divisor.show_rru_sized(mb_rru, *size)
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),
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Inst::SignedDivOrRem {
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Inst::CheckedDivOrRemSeq {
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is_div,
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is_signed,
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size,
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divisor,
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..
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} => format!(
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"s{} $rax:$rdx, {}",
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"{}{} $rax:$rdx, {}",
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if *is_signed { "s" } else { "u" },
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if *is_div { "div " } else { "rem " },
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show_ireg_sized(*divisor, mb_rru, *size),
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),
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@@ -730,12 +741,7 @@ impl ShowWithRRU for Inst {
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taken.show_rru(mb_rru),
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not_taken.show_rru(mb_rru)
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),
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Inst::OneWayJmpCond { cc, dst } => format!(
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"{} {}",
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ljustify2("j".to_string(), cc.to_string()),
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dst.show_rru(mb_rru),
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),
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Inst::JmpTable { idx, .. } => {
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Inst::JmpTableSeq { idx, .. } => {
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format!("{} {}", ljustify("br_table".into()), idx.show_rru(mb_rru))
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}
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//
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@@ -744,6 +750,9 @@ impl ShowWithRRU for Inst {
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ljustify("jmp".to_string()),
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target.show_rru(mb_rru)
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),
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Inst::TrapIf { cc, trap_code, .. } => {
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format!("j{} ; ud2 {} ;", cc.invert().to_string(), trap_code)
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}
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Inst::VirtualSPOffsetAdj { offset } => format!("virtual_sp_offset_adjust {}", offset),
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Inst::Hlt => "hlt".into(),
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Inst::Ud2 { trap_info } => format!("ud2 {}", trap_info.1),
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@@ -779,7 +788,7 @@ fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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collector.add_mod(Writable::from_reg(regs::rdx()));
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divisor.get_regs_as_uses(collector);
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}
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Inst::SignedDivOrRem { divisor, .. } => {
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Inst::CheckedDivOrRemSeq { divisor, .. } => {
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collector.add_mod(Writable::from_reg(regs::rax()));
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collector.add_mod(Writable::from_reg(regs::rdx()));
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collector.add_use(*divisor);
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@@ -871,7 +880,7 @@ fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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dest.get_regs_as_uses(collector);
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}
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Inst::JmpTable {
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Inst::JmpTableSeq {
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ref idx,
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ref tmp1,
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ref tmp2,
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@@ -886,9 +895,9 @@ fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
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| Inst::EpiloguePlaceholder
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| Inst::JmpKnown { .. }
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| Inst::JmpCond { .. }
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| Inst::OneWayJmpCond { .. }
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| Inst::Nop { .. }
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| Inst::JmpUnknown { .. }
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| Inst::TrapIf { .. }
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| Inst::VirtualSPOffsetAdj { .. }
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| Inst::Hlt
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| Inst::Ud2 { .. } => {
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@@ -977,7 +986,7 @@ fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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map_mod(mapper, dst);
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}
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Inst::Div { divisor, .. } => divisor.map_uses(mapper),
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Inst::SignedDivOrRem { divisor, .. } => {
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Inst::CheckedDivOrRemSeq { divisor, .. } => {
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map_use(mapper, divisor);
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}
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Inst::SignExtendRaxRdx { .. } => {}
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@@ -1104,7 +1113,7 @@ fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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dest.map_uses(mapper);
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}
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Inst::JmpTable {
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Inst::JmpTableSeq {
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ref mut idx,
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ref mut tmp1,
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ref mut tmp2,
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@@ -1119,9 +1128,9 @@ fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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| Inst::EpiloguePlaceholder
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| Inst::JmpKnown { .. }
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| Inst::JmpCond { .. }
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| Inst::OneWayJmpCond { .. }
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| Inst::Nop { .. }
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| Inst::JmpUnknown { .. }
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| Inst::TrapIf { .. }
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| Inst::VirtualSPOffsetAdj { .. }
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| Inst::Ud2 { .. }
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| Inst::Hlt => {
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@@ -1182,7 +1191,7 @@ impl MachInst for Inst {
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taken,
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not_taken,
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} => MachTerminator::Cond(taken.as_label().unwrap(), not_taken.as_label().unwrap()),
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&Self::JmpTable {
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&Self::JmpTableSeq {
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ref targets_for_term,
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..
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} => MachTerminator::Indirect(&targets_for_term[..]),
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