s390x: Add support for all remaining atomic operations (#3746)
This adds support for all atomic operations that were unimplemented so far in the s390x back end: - atomic_rmw operations xchg, nand, smin, smax, umin, umax - $I8 and $I16 versions of atomic_rmw and atomic_cas - little endian versions of atomic_rmw and atomic_cas All of these have to be implemented by a compare-and-swap loop; and for the $I8 and $I16 versions the actual atomic instruction needs to operate on the surrounding aligned 32-bit word. Since we cannot emit new control flow during ISLE instruction selection, these compare-and-swap loops are emitted as a single meta-instruction to be expanded at emit time. However, since there is a large number of different versions of the loop required to implement all the above operations, I've implemented a facility to allow specifying the loop bodies from within ISLE after all, by creating a vector of MInst structures that will be emitted as part of the meta-instruction. There are still restrictions, in particular instructions that are part of the loop body may not modify any virtual register. But even so, this approach looks preferable to doing everything in emit.rs. A few instructions needed in those compare-and-swap loop bodies were added as well, in particular the RxSBG family of instructions as well as the LOAD REVERSED in-register byte-swap instructions. This patch also adds filetest runtests to verify the semantics of all operations, in particular the subword and little-endian variants (those are currently only executed on s390x).
This commit is contained in:
Ulrich Weigand
@@ -112,6 +112,26 @@
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(shift_imm u8)
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(shift_reg Reg))
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;; A rotate-then-<op>-selected-bits instruction with a register
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;; in/out-operand, another register source, and three immediates.
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(RxSBG
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(op RxSBGOp)
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(rd WritableReg)
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(rn Reg)
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(start_bit u8)
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(end_bit u8)
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(rotate_amt i8))
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;; The test-only version of RxSBG, which does not modify any register
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;; but only sets the condition code.
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(RxSBGTest
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(op RxSBGOp)
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(rd Reg)
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(rn Reg)
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(start_bit u8)
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(end_bit u8)
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(rotate_amt i8))
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;; An unary operation with a register source and a register destination.
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(UnaryRR
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(op UnaryOp)
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@@ -658,6 +678,19 @@
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(rd WritableReg)
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(mem MemArg))
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;; Meta-instruction to emit a loop around a sequence of instructions.
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;; This control flow is not visible to the compiler core, in particular
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;; the register allocator. Therefore, instructions in the loop may not
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;; write to any virtual register, so any writes must use reserved hard
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;; registers (e.g. %r0, %r1). *Reading* virtual registers is OK.
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(Loop
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(body VecMInst)
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(cond Cond))
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;; Conditional branch breaking out of a loop emitted via Loop.
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(CondBreak
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(cond Cond))
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;; Marker, no-op in generated code SP "virtual offset" is adjusted. This
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;; controls how MemArg::NominalSPOffset args are lowered.
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(VirtualSPOffsetAdj
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@@ -732,6 +765,8 @@
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(Neg64Ext32)
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(PopcntByte)
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(PopcntReg)
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(BSwap32)
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(BSwap64)
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))
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;; A shift operation.
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@@ -747,6 +782,15 @@
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(AShR64)
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))
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;; A rotate-then-<op>-selected-bits operation.
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(type RxSBGOp
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(enum
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(Insert)
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(And)
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(Or)
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(Xor)
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))
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;; An integer comparison operation.
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(type CmpOp
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(enum
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@@ -1395,6 +1439,13 @@
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(_ Unit (emit (MInst.ShiftRR op dst src shift_imm shift_reg))))
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(writable_reg_to_reg dst)))
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;; Helper for emitting `MInst.RxSBGTest` instructions.
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(decl rxsbg_test (RxSBGOp Reg Reg u8 u8 i8) ProducesFlags)
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(rule (rxsbg_test op src1 src2 start_bit end_bit rotate_amt)
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(ProducesFlags.ProducesFlags (MInst.RxSBGTest op src1 src2
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start_bit end_bit rotate_amt)
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(invalid_reg)))
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;; Helper for emitting `MInst.UnaryRR` instructions.
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(decl unary_rr (Type UnaryOp Reg) Reg)
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(rule (unary_rr ty op src)
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@@ -1719,6 +1770,95 @@
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result))
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;; Helpers for instruction sequences ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Completed instruction sequence for use in MInst.Loop.
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(type VecMInst (primitive VecMInst))
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;; Partial (mutable) instruction sequence in the process of being created.
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(type VecMInstBuilder extern (enum))
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;; Create a new empty instruction sequence builder.
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(decl inst_builder_new () VecMInstBuilder)
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(extern constructor inst_builder_new inst_builder_new)
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;; Push an instruction to a sequence under construction.
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(decl inst_builder_push (VecMInstBuilder MInst) Unit)
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(extern constructor inst_builder_push inst_builder_push)
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;; Complete the sequence under construction.
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(decl inst_builder_finish (VecMInstBuilder) VecMInst)
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(extern constructor inst_builder_finish inst_builder_finish)
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;; It is not safe to write to virtual registers in the loop, so all destination
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;; registers must be real. This must be handled by the user of these helpers,
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;; so we simply verify this constraint here.
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(decl real_reg (WritableReg) WritableReg)
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(extern extractor real_reg real_reg)
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;; Similarly, because we cannot allocate temp registers, if an instruction
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;; requires matching source and destination registers, this needs to be handled
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;; by the user. Another helper to verify that constraint.
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(decl same_reg (WritableReg) Reg)
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(extern extractor same_reg same_reg (in))
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;; Push a `MInst.AluRRR` instruction to a sequence.
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(decl push_alu_reg (VecMInstBuilder ALUOp WritableReg Reg Reg) Reg)
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(rule (push_alu_reg ib op (real_reg dst) src1 src2)
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(let ((_ Unit (inst_builder_push ib (MInst.AluRRR op dst src1 src2))))
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(writable_reg_to_reg dst)))
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;; Push a `MInst.AluRUImm32Shifted` instruction to a sequence.
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(decl push_alu_uimm32shifted (VecMInstBuilder ALUOp WritableReg Reg UImm32Shifted) Reg)
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(rule (push_alu_uimm32shifted ib op (real_reg dst) (same_reg <dst) imm)
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(let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst imm))))
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(writable_reg_to_reg dst)))
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;; Push a `MInst.ShiftRR` instruction to a sequence.
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(decl push_shift (VecMInstBuilder ShiftOp WritableReg Reg u8 Reg) Reg)
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(rule (push_shift ib op (real_reg dst) src shift_imm shift_reg)
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(let ((_ Unit (inst_builder_push ib
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(MInst.ShiftRR op dst src shift_imm shift_reg))))
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(writable_reg_to_reg dst)))
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;; Push a `MInst.RxSBG` instruction to a sequence.
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(decl push_rxsbg (VecMInstBuilder RxSBGOp WritableReg Reg Reg u8 u8 i8) Reg)
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(rule (push_rxsbg ib op (real_reg dst) (same_reg <dst) src start_bit end_bit rotate_amt)
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(let ((_ Unit (inst_builder_push ib
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(MInst.RxSBG op dst src start_bit end_bit rotate_amt))))
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(writable_reg_to_reg dst)))
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;; Push a `MInst.UnaryRR` instruction to a sequence.
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(decl push_unary (VecMInstBuilder UnaryOp WritableReg Reg) Reg)
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(rule (push_unary ib op (real_reg dst) src)
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(let ((_ Unit (inst_builder_push ib (MInst.UnaryRR op dst src))))
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(writable_reg_to_reg dst)))
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;; Push a `MInst.AtomicCas32` instruction to a sequence.
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(decl push_atomic_cas32 (VecMInstBuilder WritableReg Reg MemArg) Reg)
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(rule (push_atomic_cas32 ib (real_reg dst_src1) src2 mem)
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(let ((_ Unit (inst_builder_push ib (MInst.AtomicCas32 dst_src1 src2 mem))))
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(writable_reg_to_reg dst_src1)))
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;; Push a `MInst.AtomicCas64` instruction to a sequence.
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(decl push_atomic_cas64 (VecMInstBuilder WritableReg Reg MemArg) Reg)
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(rule (push_atomic_cas64 ib (real_reg dst_src1) src2 mem)
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(let ((_ Unit (inst_builder_push ib (MInst.AtomicCas64 dst_src1 src2 mem))))
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(writable_reg_to_reg dst_src1)))
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;; Push instructions to break out of the loop if condition is met.
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(decl push_break_if (VecMInstBuilder ProducesFlags Cond) Reg)
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(rule (push_break_if ib (ProducesFlags.ProducesFlags inst result) cond)
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(let ((_1 Unit (inst_builder_push ib inst))
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(_2 Unit (inst_builder_push ib (MInst.CondBreak cond))))
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result))
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;; Emit a `MInst.Loop` instruction holding a loop body instruction sequence.
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(decl emit_loop (VecMInstBuilder Cond) Unit)
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(rule (emit_loop ib cond)
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(emit (MInst.Loop (inst_builder_finish ib) cond)))
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;; Helpers for generating register moves ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Move source register into destination. (Non-SSA form.)
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@@ -1747,6 +1887,13 @@
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(decl copy_reg (Type Reg) Reg)
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(rule (copy_reg ty reg) (writable_reg_to_reg (copy_writable_reg ty reg)))
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;; Move from memory location into destination.
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(decl emit_load (Type WritableReg MemArg) Unit)
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(rule (emit_load $I32 dst addr)
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(emit (MInst.Load32 dst addr)))
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(rule (emit_load $I64 dst addr)
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(emit (MInst.Load64 dst addr)))
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;; Helpers for generating immediate values ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -2249,6 +2396,123 @@
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(trap_if_impl cond trap_code)))
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;;;; Helpers for compare-and-swap loops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; We use the emit_loop functionality to create compare-and-swap loops.
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;; As noted there, code inside a loop emitted via emit_loop cannot write
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;; to any virtual register, only hard registers. We use the two reserved
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;; registers %r0 and %r1 in compare-and-swap loops.
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;; %r0 always holds the value currently loaded from the memory location.
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(decl casloop_val_reg () WritableReg)
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(rule (casloop_val_reg) (writable_gpr 0))
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;; %r1 is available to compute the new value to be written.
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(decl casloop_tmp_reg () WritableReg)
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(rule (casloop_tmp_reg) (writable_gpr 1))
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;; This takes a loop body for a compare-and-swap loop, completes it by
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;; adding the actual compare-and-swap instruction, and emits the initial
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;; memory load followed by the loop itself. "val" is the new value to
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;; be written if the memory location still holds the old value in %r0.
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;; The result should be passed to "casloop_result" or (in the case of
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;; subword loops) to "casloop_rotate_result".
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(decl casloop_emit (VecMInstBuilder Type MemFlags Reg Reg) Reg)
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(rule (casloop_emit ib ty flags aligned_addr val)
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(let (;; Construct a memory argument for the aligned word.
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(aligned_mem MemArg (memarg_reg_plus_off aligned_addr 0 flags))
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;; Add the compare-and-swap instruction to the builder.
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(result Reg (push_atomic_cas ib (ty_ext32 ty)
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(casloop_val_reg) val aligned_mem))
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;; Emit initial load followed by compare-and-swap loop.
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(_1 Unit (emit_load (ty_ext32 ty) (casloop_val_reg) aligned_mem))
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(_2 Unit (emit_loop ib (intcc_as_cond (IntCC.NotEqual)))))
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result))
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;; Compute the previous memory value after a (fullword) compare-and-swap loop.
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;; In the big-endian case, the value is already correct, but may need to be
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;; copied out of the hard register. In the little-endian case, we need to
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;; byte-swap since the compare-and-swap instruction is always big-endian.
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(decl casloop_result (Type MemFlags Reg) Reg)
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(rule (casloop_result (ty_32_or_64 ty) (bigendian) result)
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(copy_reg ty result))
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(rule (casloop_result (ty_32_or_64 ty) (littleendian) result)
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(bswap_reg ty result))
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;; Emit a fullword compare-and-swap loop, returning the previous memory value.
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(decl casloop (VecMInstBuilder Type MemFlags Reg Reg) Reg)
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(rule (casloop ib ty flags aligned_addr val)
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(casloop_result ty flags (casloop_emit ib ty flags aligned_addr val)))
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;; For types smaller than $I32, we have no native compare-and-swap
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;; instruction, so we need to perform the compare-and-swap loop on the
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;; surrounding aligned word. To actually operate on the target $I8 or
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;; $I16 data, that aligned word then needs to be rotated by an amount
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;; determined by the low address bits.
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;; Determine the rotate amount to bring the target data into a position
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;; in the high bytes of the enclosing $I32. Since the compare-and-swap
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;; instruction performs a big-endian memory access, this can be done by
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;; rotating (left) by "(addr & 3) * 8" bits, or "(addr << 3) & 31" bits.
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;; We can omit the "& 31" since this is implicit with a 32-bit rotate.
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(decl casloop_bitshift (Reg) Reg)
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(rule (casloop_bitshift addr)
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(lshl_imm $I32 addr 3))
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;; The address of the surrounding 32-bit word, by masking off low bits.
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(decl casloop_aligned_addr (Reg) Reg)
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(rule (casloop_aligned_addr addr)
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(and_uimm16shifted $I64 addr (uimm16shifted 0xfffc 0)))
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;; Push an instruction sequence to rotate a value loaded from memory
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;; to the well-defined location: the high bytes in case of a big-endian
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;; memory operation, and the low bytes in the little-endian case.
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;; (This is somewhat arbitary but chosen to allow the most efficient
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;; sequences to compute the various atomic operations.)
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;; Note that $I8 accesses always use the big-endian case.
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(decl casloop_rotate_in (VecMInstBuilder Type MemFlags Reg Reg) Reg)
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(rule (casloop_rotate_in ib $I8 _ bitshift val)
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(push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 bitshift))
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(rule (casloop_rotate_in ib $I16 (bigendian) bitshift val)
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(push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 bitshift))
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(rule (casloop_rotate_in ib $I16 (littleendian) bitshift val)
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(push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 16 bitshift))
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;; The inverse operation: rotate values back to the original memory order.
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;; This can be done by simply using the negated shift count. As an extra
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;; optimization, we note that in the $I16 case the shift count can only
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;; take the values 0 or 16, both of which negate to themselves (mod 32),
|
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;; so the explicit negation operation can be omitted here.
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(decl casloop_rotate_out (VecMInstBuilder Type MemFlags Reg Reg) Reg)
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(rule (casloop_rotate_out ib $I8 _ bitshift val)
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(push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 (neg_reg $I32 bitshift)))
|
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(rule (casloop_rotate_out ib $I16 (bigendian) bitshift val)
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(push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 bitshift))
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(rule (casloop_rotate_out ib $I16 (littleendian) bitshift val)
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(push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 16 bitshift))
|
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;; Compute the previous memory value after a subword compare-and-swap loop.
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;; This is similar to casloop_rotate_in, but brings the value to the *low*
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;; bytes. This can be achieved simply by adding the type size to the rotate
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;; amount, which can be done within the same instruction. In the little-
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;; endian case, we also need to byte-swap the result. Since we only have
|
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;; a 32-bit byte-swap instruction, we load the value to the high bytes in
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;; this case before performing the 32-bit byte-swap.
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(decl casloop_rotate_result (Type MemFlags Reg Reg) Reg)
|
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(rule (casloop_rotate_result $I8 _ bitshift result)
|
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(rot_imm_reg $I32 result 8 bitshift))
|
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(rule (casloop_rotate_result $I16 (bigendian) bitshift result)
|
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(rot_imm_reg $I32 result 16 bitshift))
|
||||
(rule (casloop_rotate_result $I16 (littleendian) bitshift result)
|
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(bswap_reg $I32 (rot_reg $I32 result bitshift)))
|
||||
|
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;; Emit a subword compare-and-swap loop, returning the previous memory value.
|
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(decl casloop_subword (VecMInstBuilder Type MemFlags Reg Reg Reg) Reg)
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(rule (casloop_subword ib ty flags aligned_addr bitshift val)
|
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(casloop_rotate_result ty flags bitshift
|
||||
(casloop_emit ib ty flags aligned_addr val)))
|
||||
|
||||
|
||||
;; Helpers for generating `clz` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
;; Count leading zeroes. For a zero input, return the specified value.
|
||||
@@ -2497,6 +2761,9 @@
|
||||
(decl xor_mem (Type Reg MemArg) Reg)
|
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(rule (xor_mem ty x y) (alu_rx ty (aluop_xor ty) x y))
|
||||
|
||||
(decl push_xor_uimm32shifted (VecMInstBuilder Type WritableReg Reg UImm32Shifted) Reg)
|
||||
(rule (push_xor_uimm32shifted ib ty dst src imm)
|
||||
(push_alu_uimm32shifted ib (aluop_xor ty) dst src imm))
|
||||
|
||||
;; Helpers for generating `not` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@@ -2508,6 +2775,13 @@
|
||||
(xor_uimm32shifted ty x (uimm32shifted 0xffffffff 0))
|
||||
(uimm32shifted 0xffffffff 32)))
|
||||
|
||||
(decl push_not_reg (VecMInstBuilder Type WritableReg Reg) Reg)
|
||||
(rule (push_not_reg ib (gpr32_ty ty) dst src)
|
||||
(push_xor_uimm32shifted ib ty dst src (uimm32shifted 0xffffffff 0)))
|
||||
(rule (push_not_reg ib (gpr64_ty ty) dst src)
|
||||
(let ((val Reg (push_xor_uimm32shifted ib ty dst src (uimm32shifted 0xffffffff 0))))
|
||||
(push_xor_uimm32shifted ib ty dst val (uimm32shifted 0xffffffff 32))))
|
||||
|
||||
|
||||
;; Helpers for generating `and_not` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@@ -2573,6 +2847,19 @@
|
||||
(rule (neg_reg_sext32 ty x) (unary_rr ty (unaryop_neg_sext32 ty) x))
|
||||
|
||||
|
||||
;; Helpers for generating `bswap` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(decl unaryop_bswap (Type) UnaryOp)
|
||||
(rule (unaryop_bswap $I32) (UnaryOp.BSwap32))
|
||||
(rule (unaryop_bswap $I64) (UnaryOp.BSwap64))
|
||||
|
||||
(decl bswap_reg (Type Reg) Reg)
|
||||
(rule (bswap_reg ty x) (unary_rr ty (unaryop_bswap ty) x))
|
||||
|
||||
(decl push_bswap_reg (VecMInstBuilder Type WritableReg Reg) Reg)
|
||||
(rule (push_bswap_reg ib ty dst src) (push_unary ib (unaryop_bswap ty) dst src))
|
||||
|
||||
|
||||
;; Helpers for generating `rot` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(decl shiftop_rot (Type) ShiftOp)
|
||||
@@ -2587,6 +2874,14 @@
|
||||
(rule (rot_imm ty x shift_imm)
|
||||
(shift_rr ty (shiftop_rot ty) x shift_imm (zero_reg)))
|
||||
|
||||
(decl rot_imm_reg (Type Reg u8 Reg) Reg)
|
||||
(rule (rot_imm_reg ty x shift_imm shift_reg)
|
||||
(shift_rr ty (shiftop_rot ty) x shift_imm shift_reg))
|
||||
|
||||
(decl push_rot_imm_reg (VecMInstBuilder Type WritableReg Reg u8 Reg) Reg)
|
||||
(rule (push_rot_imm_reg ib ty dst src shift_imm shift_reg)
|
||||
(push_shift ib (shiftop_rot ty) dst src shift_imm shift_reg))
|
||||
|
||||
|
||||
;; Helpers for generating `lshl` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
@@ -2663,6 +2958,17 @@
|
||||
(rule (atomic_rmw_add $I64 src mem) (atomic_rmw_impl $I64 (ALUOp.Add64) src mem))
|
||||
|
||||
|
||||
;; Helpers for generating `atomic_cas` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(decl atomic_cas_impl (Type Reg Reg MemArg) Reg)
|
||||
(rule (atomic_cas_impl $I32 src1 src2 mem) (atomic_cas32 src1 src2 mem))
|
||||
(rule (atomic_cas_impl $I64 src1 src2 mem) (atomic_cas64 src1 src2 mem))
|
||||
|
||||
(decl push_atomic_cas (VecMInstBuilder Type WritableReg Reg MemArg) Reg)
|
||||
(rule (push_atomic_cas ib $I32 src1 src2 mem) (push_atomic_cas32 ib src1 src2 mem))
|
||||
(rule (push_atomic_cas ib $I64 src1 src2 mem) (push_atomic_cas64 ib src1 src2 mem))
|
||||
|
||||
|
||||
;; Helpers for generating `fadd` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
(decl fpuop2_add (Type) FPUOp2)
|
||||
|
||||
Reference in New Issue
Block a user