Remove the widening_pairwise_dot_product_s clif instruction (#5889)
This was added for the wasm SIMD proposal but I've been poking around at this recently and the instruction can instead be represented by its component parts with the same semantics I believe. This commit removes the instruction and instead represents it with the existing `iadd_pairwise` instruction (among others) and updates backends to with new pattern matches to have the same codegen as before. This interestingly entirely removed the codegen rule with no replacement on the AArch64 backend as the existing rules all existed to produce the same codegen.
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@@ -3134,41 +3134,6 @@ pub(crate) fn define(
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.operands_out(vec![a]),
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);
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let I16x8 = &TypeVar::new(
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"I16x8",
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"A SIMD vector type containing 8 integer lanes each 16 bits wide.",
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TypeSetBuilder::new()
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.ints(16..16)
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.simd_lanes(8..8)
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.includes_scalars(false)
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.build(),
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);
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let x = &Operand::new("x", I16x8);
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let y = &Operand::new("y", I16x8);
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let a = &Operand::new("a", &I16x8.merge_lanes());
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ig.push(
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Inst::new(
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"widening_pairwise_dot_product_s",
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r#"
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Takes corresponding elements in `x` and `y`, performs a sign-extending length-doubling
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multiplication on them, then adds adjacent pairs of elements to form the result. For
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example, if the input vectors are `[x3, x2, x1, x0]` and `[y3, y2, y1, y0]`, it produces
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the vector `[r1, r0]`, where `r1 = sx(x3) * sx(y3) + sx(x2) * sx(y2)` and
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`r0 = sx(x1) * sx(y1) + sx(x0) * sx(y0)`, and `sx(n)` sign-extends `n` to twice its width.
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This will double the lane width and halve the number of lanes. So the resulting
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vector has the same number of bits as `x` and `y` do (individually).
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See <https://github.com/WebAssembly/simd/pull/127> for background info.
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"#,
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&formats.binary,
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)
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.operands_in(vec![x, y])
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.operands_out(vec![a]),
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);
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let IntTo = &TypeVar::new(
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"IntTo",
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"A larger integer type with the same number of lanes",
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