diff --git a/filetests/regalloc/constraints.cton b/filetests/regalloc/constraints.cton
index e88bcc514c..c6108b0673 100644
--- a/filetests/regalloc/constraints.cton
+++ b/filetests/regalloc/constraints.cton
@@ -13,3 +13,16 @@ ebb0:
     v2 = isub v0, v1
     return v2
 }
+
+; Fixed register constraint.
+function %fixed_op() -> i32 {
+ebb0:
+    ; check: ,%rax]
+    ; sameln: $v0 = iconst.i32 12
+    v0 = iconst.i32 12
+    v1 = iconst.i32 13
+    ; The dynamic shift amount must be in %rcx
+    ; check: regmove $v0, %rax -> %rcx
+    v2 = ishl v1, v0
+    return v2
+}
diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index e4e5a6599f..f61e88e9b7 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -371,7 +371,8 @@ impl<'a> Context<'a> {
             for (op, lv) in constraints.outs.iter().zip(defs) {
                 if let ConstraintKind::Tied(num) = op.kind {
                     let arg = dfg.inst_args(inst)[num as usize];
-                    locations[lv.value] = locations[arg];
+                    let reg = self.divert.reg(arg, locations);
+                    locations[lv.value] = ValueLoc::Reg(reg);
                 }
             }
         }