diff --git a/cranelift/codegen/src/isa/x64/abi.rs b/cranelift/codegen/src/isa/x64/abi.rs
index 0da1a5cd3d..543421a86a 100644
--- a/cranelift/codegen/src/isa/x64/abi.rs
+++ b/cranelift/codegen/src/isa/x64/abi.rs
@@ -1,20 +1,17 @@
 //! Implementation of the standard x64 ABI.
 
-use log::trace;
-use regalloc::{RealReg, Reg, RegClass, Set, SpillSlot, Writable};
-
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use std::mem;
-
 use crate::binemit::Stackmap;
 use crate::ir::{self, types, types::*, ArgumentExtension, StackSlot, Type};
 use crate::isa::{x64::inst::*, CallConv};
 use crate::machinst::*;
 use crate::settings;
 use crate::{CodegenError, CodegenResult};
-
+use alloc::boxed::Box;
+use alloc::vec::Vec;
 use args::*;
+use log::trace;
+use regalloc::{RealReg, Reg, RegClass, Set, SpillSlot, Writable};
+use std::mem;
 
 /// This is the limit for the size of argument and return-value areas on the
 /// stack. We place a reasonable limit here to avoid integer overflow issues
diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index a08ea230cd..7cd6a2caef 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -1,18 +1,13 @@
 //! Instruction operand sub-components (aka "parts"): definitions and printing.
 
-use std::fmt;
-use std::string::{String, ToString};
-
-use regalloc::{RealRegUniverse, Reg, RegClass, RegUsageCollector, RegUsageMapper};
-
+use super::regs::{self, show_ireg_sized};
+use super::EmitState;
 use crate::ir::condcodes::{FloatCC, IntCC};
 use crate::machinst::*;
-
-use super::{
-    regs::{self, show_ireg_sized},
-    EmitState,
-};
 use core::fmt::Debug;
+use regalloc::{RealRegUniverse, Reg, RegClass, RegUsageCollector, RegUsageMapper};
+use std::fmt;
+use std::string::{String, ToString};
 
 /// A possible addressing mode (amode) that can be used in instructions.
 /// These denote a 64-bit value only.
diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
index 1d28e64557..b966398804 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
@@ -9,10 +9,9 @@
 //! (cd cranelift/codegen && \
 //! RUST_BACKTRACE=1 cargo test isa::x64::inst::test_x64_insn_encoding_and_printing -- --nocapture)
 
-use alloc::vec::Vec;
-
 use super::*;
 use crate::isa::test_utils;
+use alloc::vec::Vec;
 
 #[test]
 fn test_x64_emit() {
diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs
index 3e183989a9..14fd91ccdc 100644
--- a/cranelift/codegen/src/isa/x64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/x64/inst/mod.rs
@@ -4,21 +4,20 @@
 #![allow(non_snake_case)]
 #![allow(non_camel_case_types)]
 
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use std::fmt;
-use std::string::{String, ToString};
-
-use regalloc::RegUsageCollector;
-use regalloc::{RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable};
-use smallvec::SmallVec;
-
 use crate::binemit::{CodeOffset, Stackmap};
 use crate::ir::types::*;
 use crate::ir::{ExternalName, Opcode, SourceLoc, TrapCode, Type};
 use crate::machinst::*;
-use crate::settings::Flags;
-use crate::{settings, CodegenError, CodegenResult};
+use crate::{settings, settings::Flags, CodegenError, CodegenResult};
+use alloc::boxed::Box;
+use alloc::vec::Vec;
+use regalloc::{
+    RealRegUniverse, Reg, RegClass, RegUsageCollector, RegUsageMapper, SpillSlot, VirtualReg,
+    Writable,
+};
+use smallvec::SmallVec;
+use std::fmt;
+use std::string::{String, ToString};
 
 pub mod args;
 mod emit;
diff --git a/cranelift/codegen/src/isa/x64/inst/regs.rs b/cranelift/codegen/src/isa/x64/inst/regs.rs
index 4f23ab11b0..5cc9a83295 100644
--- a/cranelift/codegen/src/isa/x64/inst/regs.rs
+++ b/cranelift/codegen/src/isa/x64/inst/regs.rs
@@ -10,13 +10,10 @@
 //! Also, they will have to be ABI dependent.  Need to find a way to avoid constructing a universe
 //! for each function we compile.
 
+use crate::{machinst::pretty_print::ShowWithRRU, settings};
 use alloc::vec::Vec;
-use std::string::String;
-
 use regalloc::{RealReg, RealRegUniverse, Reg, RegClass, RegClassInfo, NUM_REG_CLASSES};
-
-use crate::machinst::pretty_print::ShowWithRRU;
-use crate::settings;
+use std::string::String;
 
 // Hardware encodings for a few registers.
 
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 9250c72440..573cc1da14 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -2,31 +2,26 @@
 
 #![allow(non_snake_case)]
 
-use log::trace;
-use regalloc::{Reg, RegClass, Writable};
-use smallvec::SmallVec;
-
-use crate::ir::types;
 use crate::ir::types::*;
-use crate::ir::Inst as IRInst;
 use crate::ir::{
-    condcodes::FloatCC, condcodes::IntCC, AbiParam, ArgumentPurpose, ExternalName, InstructionData,
-    LibCall, Opcode, Signature, TrapCode, Type,
+    condcodes::FloatCC, condcodes::IntCC, types, AbiParam, ArgumentPurpose, ExternalName,
+    Inst as IRInst, InstructionData, LibCall, Opcode, Signature, TrapCode, Type,
 };
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use cranelift_codegen_shared::condcodes::CondCode;
-use std::convert::TryFrom;
-
-use crate::machinst::lower::*;
-use crate::machinst::*;
-use crate::result::CodegenResult;
-use crate::settings::Flags;
-
 use crate::isa::x64::abi::*;
 use crate::isa::x64::inst::args::*;
 use crate::isa::x64::inst::*;
 use crate::isa::{x64::X64Backend, CallConv};
+use crate::machinst::lower::*;
+use crate::machinst::*;
+use crate::result::CodegenResult;
+use crate::settings::Flags;
+use alloc::boxed::Box;
+use alloc::vec::Vec;
+use cranelift_codegen_shared::condcodes::CondCode;
+use log::trace;
+use regalloc::{Reg, RegClass, Writable};
+use smallvec::SmallVec;
+use std::convert::TryFrom;
 use target_lexicon::Triple;
 
 /// Context passed to all lowering functions.
diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
index 271542378a..c54cfe6ad6 100644
--- a/cranelift/codegen/src/isa/x64/mod.rs
+++ b/cranelift/codegen/src/isa/x64/mod.rs
@@ -1,21 +1,17 @@
 //! X86_64-bit Instruction Set Architecture.
 
-use alloc::boxed::Box;
-
-use regalloc::RealRegUniverse;
-use target_lexicon::Triple;
-
-use crate::ir::condcodes::IntCC;
-use crate::ir::Function;
+use super::TargetIsa;
+use crate::ir::{condcodes::IntCC, Function};
+use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings};
 use crate::isa::Builder as IsaBuilder;
-use crate::machinst::pretty_print::ShowWithRRU;
-use crate::machinst::{compile, MachBackend, MachCompileResult, TargetIsaAdapter, VCode};
+use crate::machinst::{
+    compile, pretty_print::ShowWithRRU, MachBackend, MachCompileResult, TargetIsaAdapter, VCode,
+};
 use crate::result::CodegenResult;
 use crate::settings::{self as shared_settings, Flags};
-
-use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings};
-
-use super::TargetIsa;
+use alloc::boxed::Box;
+use regalloc::RealRegUniverse;
+use target_lexicon::Triple;
 
 mod abi;
 mod inst;