diff --git a/cranelift/codegen/meta/src/cdsl/instructions.rs b/cranelift/codegen/meta/src/cdsl/instructions.rs
index 40491d9cec..42cf0e3af4 100644
--- a/cranelift/codegen/meta/src/cdsl/instructions.rs
+++ b/cranelift/codegen/meta/src/cdsl/instructions.rs
@@ -86,8 +86,6 @@ pub(crate) struct InstructionContent {
     pub other_side_effects: bool,
     /// Does this instruction write to CPU flags?
     pub writes_cpu_flags: bool,
-    /// Should this opcode be considered to clobber all live registers, during regalloc?
-    pub clobbers_all_regs: bool,
 }
 
 impl InstructionContent {
@@ -150,7 +148,6 @@ pub(crate) struct InstructionBuilder {
     can_store: bool,
     can_trap: bool,
     other_side_effects: bool,
-    clobbers_all_regs: bool,
 }
 
 impl InstructionBuilder {
@@ -172,7 +169,6 @@ impl InstructionBuilder {
             can_store: false,
             can_trap: false,
             other_side_effects: false,
-            clobbers_all_regs: false,
         }
     }
 
@@ -298,7 +294,6 @@ impl InstructionBuilder {
             can_trap: self.can_trap,
             other_side_effects: self.other_side_effects,
             writes_cpu_flags,
-            clobbers_all_regs: self.clobbers_all_regs,
         })
     }
 }
diff --git a/cranelift/codegen/meta/src/gen_inst.rs b/cranelift/codegen/meta/src/gen_inst.rs
index c8c91ad604..fb10dff8cb 100644
--- a/cranelift/codegen/meta/src/gen_inst.rs
+++ b/cranelift/codegen/meta/src/gen_inst.rs
@@ -524,13 +524,6 @@ fn gen_opcodes(all_inst: &AllInstructions, fmt: &mut Formatter) {
             "Does this instruction write to CPU flags?",
             fmt,
         );
-        gen_bool_accessor(
-            all_inst,
-            |inst| inst.clobbers_all_regs,
-            "clobbers_all_regs",
-            "Should this opcode be considered to clobber all the registers, during regalloc?",
-            fmt,
-        );
     });
     fmt.line("}");
     fmt.empty_line();