Enable the simd_i16x8_q15mulr_sat_s test on AArch64

2021-06-23 13:51:17 +01:00
parent d42c8692bc
commit 98f1ac789e
11 changed files with 110 additions and 22 deletions
--- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs
@@ -2228,6 +2228,14 @@ impl MachInstEmit for Inst {
                    VecALUOp::Zip1 => (0b01001110_00_0 | enc_size << 1, 0b001110),
                    VecALUOp::Smull => (0b000_01110_00_1 | enc_size << 1, 0b110000),
                    VecALUOp::Smull2 => (0b010_01110_00_1 | enc_size << 1, 0b110000),
+                    VecALUOp::Sqrdmulh => {
+                        debug_assert!(
+                            size.lane_size() == ScalarSize::Size16
+                                || size.lane_size() == ScalarSize::Size32
+                        );
+
+                        (0b001_01110_00_1 | enc_size << 1, 0b101101)
+                    }
                };
                let top11 = match alu_op {
                    VecALUOp::Smull | VecALUOp::Smull2 => top11,