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Enable the simd_i16x8_q15mulr_sat_s test on AArch64

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Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
2021-06-23 13:51:17 +01:00
parent d42c8692bc
commit 98f1ac789e
11 changed files with 110 additions and 22 deletions
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8
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -2228,6 +2228,14 @@ impl MachInstEmit for Inst {
VecALUOp::Zip1 => (0b01001110_00_0 | enc_size << 1, 0b001110),
VecALUOp::Smull => (0b000_01110_00_1 | enc_size << 1, 0b110000),
VecALUOp::Smull2 => (0b010_01110_00_1 | enc_size << 1, 0b110000),
VecALUOp::Sqrdmulh => {
debug_assert!(
size.lane_size() == ScalarSize::Size16
|| size.lane_size() == ScalarSize::Size32
);
(0b001_01110_00_1 | enc_size << 1, 0b101101)
}
};
let top11 = match alu_op {
VecALUOp::Smull | VecALUOp::Smull2 => top11,

24
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -3610,6 +3610,30 @@ fn test_aarch64_binemit() {
"smull2 v8.2d, v12.4s, v14.4s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Sqrdmulh,
rd: writable_vreg(31),
rn: vreg(0),
rm: vreg(31),
size: VectorSize::Size16x8,
},
"1FB47F6E",
"sqrdmulh v31.8h, v0.8h, v31.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Sqrdmulh,
rd: writable_vreg(7),
rn: vreg(7),
rm: vreg(23),
size: VectorSize::Size32x2,
},
"E7B4B72E",
"sqrdmulh v7.2s, v7.2s, v23.2s",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Not,

3
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -311,6 +311,8 @@ pub enum VecALUOp {
Smull,
/// Signed multiply long (high halves)
Smull2,
/// Signed saturating rounding doubling multiply returning high half
Sqrdmulh,
}
/// A Vector miscellaneous operation with two registers.
@@ -3980,6 +3982,7 @@ impl Inst {
VecALUOp::Zip1 => ("zip1", size),
VecALUOp::Smull => ("smull", size),
VecALUOp::Smull2 => ("smull2", size),
VecALUOp::Sqrdmulh => ("sqrdmulh", size),
};
let rd_size = match alu_op {
VecALUOp::Umlal | VecALUOp::Smull | VecALUOp::Smull2 => size.widen(),

39
cranelift/codegen/src/isa/aarch64/lower_inst.rs
View File

@@ -1650,8 +1650,6 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
panic!("table_addr should have been removed by legalization!");
}
Opcode::ConstAddr => unimplemented!(),
Opcode::Nop => {
// Nothing.
}
@@ -2684,11 +2682,6 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
});
}
Opcode::Vsplit | Opcode::Vconcat => {
// TODO
panic!("Vector ops not implemented.");
}
Opcode::Isplit => {
assert_eq!(
ctx.input_ty(insn, 0),
@@ -3524,9 +3517,35 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}
},
Opcode::FcvtLowFromSint => unimplemented!("FcvtLowFromSint"),
Opcode::FvpromoteLow => unimplemented!("FvpromoteLow"),
Opcode::Fvdemote => unimplemented!("Fvdemote"),
Opcode::SqmulRoundSat => {
let ty = ty.unwrap();
if !ty.is_vector() || (ty.lane_type() != I16 && ty.lane_type() != I32) {
return Err(CodegenError::Unsupported(format!(
"Unsupported type: {:?}",
ty
)));
}
let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
ctx.emit(Inst::VecRRR {
alu_op: VecALUOp::Sqrdmulh,
rd,
rn,
rm,
size: VectorSize::from_ty(ty),
});
}
Opcode::ConstAddr
| Opcode::FcvtLowFromSint
| Opcode::Fvdemote
| Opcode::FvpromoteLow
| Opcode::Vconcat
| Opcode::Vsplit => unimplemented!("lowering {}", op),
}
Ok(())

19
cranelift/codegen/src/isa/s390x/lower.rs
View File

@@ -2458,11 +2458,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}
Opcode::TlsValue => {
panic!("Thread-local storage support not implemented!");
unimplemented!("Thread-local storage support not implemented!");
}
Opcode::GetPinnedReg | Opcode::SetPinnedReg => {
panic!("Pinned register support not implemented!");
unimplemented!("Pinned register support not implemented!");
}
Opcode::Icmp => {
@@ -2679,10 +2679,10 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let ty = ty.unwrap();
assert!(is_valid_atomic_transaction_ty(ty));
if endianness == Endianness::Little {
panic!("Little-endian atomic operations not implemented");
unimplemented!("Little-endian atomic operations not implemented");
}
if ty_bits(ty) < 32 {
panic!("Sub-word atomic operations not implemented");
unimplemented!("Sub-word atomic operations not implemented");
}
let op = inst_common::AtomicRmwOp::from(ctx.data(insn).atomic_rmw_op().unwrap());
let (alu_op, rn) = match op {
@@ -2701,7 +2701,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
});
(choose_32_64(ty, ALUOp::Add32, ALUOp::Add64), tmp.to_reg())
}
_ => panic!("AtomicRmw operation type {:?} not implemented", op),
_ => unimplemented!("AtomicRmw operation type {:?} not implemented", op),
};
let mem = MemArg::reg(addr, flags);
ctx.emit(Inst::AtomicRmw {
@@ -2721,10 +2721,10 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
let ty = ty.unwrap();
assert!(is_valid_atomic_transaction_ty(ty));
if endianness == Endianness::Little {
panic!("Little-endian atomic operations not implemented");
unimplemented!("Little-endian atomic operations not implemented");
}
if ty_bits(ty) < 32 {
panic!("Sub-word atomic operations not implemented");
unimplemented!("Sub-word atomic operations not implemented");
}
let mem = MemArg::reg(addr, flags);
ctx.emit(Inst::gen_move(rd, rm, ty));
@@ -2865,13 +2865,14 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::UwidenLow
| Opcode::UwidenHigh
| Opcode::WideningPairwiseDotProductS
| Opcode::SqmulRoundSat
| Opcode::FvpromoteLow
| Opcode::Fvdemote => {
// TODO
panic!("Vector ops not implemented.");
unimplemented!("Vector ops not implemented.");
}
Opcode::Isplit | Opcode::Iconcat => panic!("Wide integer ops not implemented."),
Opcode::Isplit | Opcode::Iconcat => unimplemented!("Wide integer ops not implemented."),
Opcode::Spill
| Opcode::Fill

2
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -6001,6 +6001,8 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
unimplemented!("Vector split/concat ops not implemented.");
}
Opcode::SqmulRoundSat => unimplemented!("unimplemented lowering for opcode {:?}", op),
// Opcodes that should be removed by legalization. These should
// eventually be removed if/when we replace in-situ legalization with
// something better.