diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 8fd602fe39..53546de07f 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -430,18 +430,16 @@ impl<'a> Context<'a> {
                          locations: &EntityMap<Value, ValueLoc>) {
         for (abi, &value) in abi_types.iter().zip(dfg.inst_variable_args(inst)) {
             if let ArgumentLoc::Reg(reg) = abi.location {
-                let cur_reg = self.divert.reg(value, locations);
-                if reg != cur_reg {
-                    if let Affinity::Reg(rci) =
-                        self.liveness
-                            .get(value)
-                            .expect("ABI register must have live range")
-                            .affinity {
-                        let rc = self.reginfo.rc(rci);
-                        self.solver.reassign_in(value, rc, cur_reg, reg);
-                    } else {
-                        panic!("ABI argument {} should be in a register", value);
-                    }
+                if let Affinity::Reg(rci) =
+                    self.liveness
+                        .get(value)
+                        .expect("ABI register must have live range")
+                        .affinity {
+                    let rc = self.reginfo.rc(rci);
+                    let cur_reg = self.divert.reg(value, locations);
+                    self.solver.reassign_in(value, rc, cur_reg, reg);
+                } else {
+                    panic!("ABI argument {} should be in a register", value);
                 }
             }
         }
diff --git a/lib/cretonne/src/regalloc/solver.rs b/lib/cretonne/src/regalloc/solver.rs
index 89aee41317..d94cf3e72d 100644
--- a/lib/cretonne/src/regalloc/solver.rs
+++ b/lib/cretonne/src/regalloc/solver.rs
@@ -364,13 +364,15 @@ impl Solver {
         }
         self.regs_in.free(rc, from);
         self.regs_out.take(rc, to);
-        self.assignments
-            .insert(Assignment {
-                        value,
-                        rc,
-                        from,
-                        to,
-                    });
+        if from != to {
+            self.assignments
+                .insert(Assignment {
+                            value,
+                            rc,
+                            from,
+                            to,
+                        });
+        }
     }
 
     /// Add a variable representing an input side value with an existing register assignment.